Frank Feustel

COIL INDUCTOR

Wafer with improved plating current distribution

Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities

Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structure

Wafer with improved plating current distribution

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS

Restricted stress regions formed in the contact level of a semiconductor device

Method for increasing penetration depth of drain and source implantation species for a given gate height

SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER

Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantation

Performance Enhancement in Metallization Systems of Microstructure Devices by Incorporating an Intermediate Barrier Layer

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE

Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal features

Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction

Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime

Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

Method of reducing contamination by providing a removable polymer protection film during microstructure processing

Nano imprint technique with increased flexibility with respect to alignment and feature shaping

Fabricating vias of different size of a semiconductor device by splitting the via patterning process

RECESSED INTERLAYER DIELECTRIC IN A METALLIZATION STRUCTURE OF A SEMICONDUCTOR DEVICE

Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer

HIGH-ASPECT RATIO CONTACT ELEMENT WITH SUPERIOR SHAPE IN A SEMICONDUCTOR DEVICE FOR IMPROVING LINER DEPOSITION

ENHANCED ELECTROMIGRATION PERFORMANCE OF COPPER LINES IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY SURFACE ALLOYING

Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge

Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices

Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices

Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom

Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size

Local silicidation of via bottoms in metallization systems of semiconductor devices

Metallization system of a semiconductor device comprising extra-tapered transition vias

Built-in compliance in test structures for leakage and dielectric breakdown of dielectric materials of metallization systems of semiconductor devices

PERFORMANCE ENHANCEMENT IN METALLIZATION SYSTEMS OF MICROSTRUCTURE DEVICES BY INCORPORATING GRAIN SIZE INCREASING METAL FEATURES

MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH AIR GAPS FORMED COMMONLY WITH VIAS

RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE

Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer

USING A CAP LAYER IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES AS A CMP AND ETCH STOP LAYER

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

Semiconductor device comprising a carbon-based material for through hole vias

Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

METHOD FOR REDUCING METAL IRREGULARITIES IN ADVANCED METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES

MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES

REDUCTION OF METAL SILICIDE DIFFUSION IN A SEMICONDUCTOR DEVICE BY PROTECTING SIDEWALLS OF AN ACTIVE REGION

Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material

Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics

Method for increasing penetration depth of drain and source implantation species for a given gate height

Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor

SELF-ALIGNED CONTACT STRUCTURE IN A SEMICONDUCTOR DEVICE

SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME

Hybrid contact structure with low aspect ratio contacts in a semiconductor device

Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach

Reducing copper defects during a wet chemical cleaning of exposed copper surfaces in a metallization layer of a semiconductor device

DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS

SIDEWALL PROTECTION LAYER

Semiconductor structure comprising an electrically conductive feature and method of forming a semiconductor structure

SEMICONDUCTOR DEVICE HAVING A LOCALLY ENHANCED ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE

Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines

SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME

SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING THE SAME

Method for preventing the formation of electrical shorts via contact ILD voids

Unified test structure for stress migration tests

Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devices

METHOD FOR THE PROTECTION OF METAL LAYERS AGAINST EXTERNAL CONTAMINATION

Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias

Method of selectively forming a conductive barrier layer by ALD

Method and test structure for estimating focus settings in a lithography process based on CD measurements

SYSTEM AND METHOD FOR REDUCING COLLATERAL TRANSPORT-INDUCED DAMAGE DURING MICROSTRUCTURE PROCESSING

Test structure for OPC-related shorts between lines in a semiconductor device

Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics

Field effect transistor having a stressed contact etch stop layer with reduced conformality

Method of reducing contamination by providing a removable polymer protection film during microstructure processing

Method of forming an etch indicator layer for reducing etch non-uniformities

Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edge

METHOD FOR INCREASING THE PLANARITY OF A SURFACE TOPOGRAPHY IN A MICROSTRUCTURE

Nano imprint technique with increased flexibility with respect to alignment and feature shaping

Test structure for monitoring leakage currents in a metallization layer

METHOD AND TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS CAUSED BY POROUS BARRIER MATERIALS

Method of forming electrically conductive lines in an integrated circuit

Technique for forming copper-containing lines embedded in a low-k dielectric by providing a stiffening layer

Technique for enhancing thermal and mechanical characteristics of an underfill material of a substrate/die assembly

Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging