Inventor profile of:

Bilal Khalaf

City:

Folsom, California

Country:

United States

Published Applications:

25

Last publication date:

2026-04-30

Top Assignees for applications by Bilal Khalaf

The entities that hold a legal rights for patent applications filed by inventor Khalaf Bilal:

Recent patent applications by Khalaf Bilal

Bilal Khalaf from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-30
US20260116645A1
Performing operations; transporting

APPARATUS TO HOLD ELECTRICAL COMPONENTS THAT ACCOMMODATES MULTIPLE ELECTRICAL COMPONENT SIZES

#2 | 2026-01-29
US20260033384A1
Electricity

METHODS AND SYSTEMS FOR CONTROLLING HEIGHTS OF DEVICE PACKAGES

#3 | 2024-09-26
US20240321609A1
Electricity

METHODS AND SYSTEMS FOR CONTROLLING UNDERFILL BLEED-OUT IN SEMICONDUCTOR PACKAGING

#4 | 2024-05-30
US20240179844A1
Electricity

REDUCING PRINTED CIRCUIT BOARD AREA FOR SINGLE-SIDED PRINTED CIRCUIT BOARD

#5 | 2022-07-14
US20220223487A1
Electricity

Embedded component and methods of making the same

#6 | 2022-06-09
US20220181306A1
Electricity

Microelectronic packages having a die stack and a device within the footprint of the die stack

#7 | 2021-09-23
US20210298183A1
Electricity

Buried electrical debug access port

#8 | 2021-07-01
US20210202442A1
Electricity

Microelectronic packages having a die stack and a device within the footprint of the die stack

#9 | 2021-03-11
US20210074668A1
Electricity

Electronic device packages and methods for maximizing electrical current to dies and minimizing bond finger size

#10 | 2020-12-03
US20200381406A1
Electricity

High density die package configuration on system boards

#11 | 2020-07-16
US20200227393A1
Electricity

System in package with interconnected modules

#12 | 2020-04-16
US20200119467A1
Electricity

Solderless BGA interconnect

#13 | 2020-04-16
US20200118961A1
Electricity

Dual head capillary design for vertical wire bond

#14 | 2019-12-05
US20190371687A1
Electricity

Embedded component and methods of making the same

#15 | 2019-09-12
US20190279919A1
Electricity

Through mold via (TMV) using stacked modular mold rings

#16 | 2019-06-13
US20190181072A1
Electricity

Compact wirebonding in stacked-chip system in package, and methods of making same

#17 | 2019-01-03
US20190006340A1
Electricity

I/O layout footprint for multiple 1LM/2LM configurations

#18 | 2019-01-03
US20190006331A1
Electricity

ELECTRONICS PACKAGE DEVICES WITH THROUGH-SUBSTRATE-VIAS HAVING PITCHES INDEPENDENT OF SUBSTRATE THICKNESS

#19 | 2018-10-04
US20180286833A1
Electricity

Microelectronics package providing increased memory component density

#20 | 2018-05-17
US20180138133A1
Electricity

Packaged integrated circuit device with cantilever structure

#21 | 2017-10-05
US20170285097A1
Physics

Buried electrical debug access port

#22 | 2017-07-13
US20170200685A1
Electricity

Microelectronic package debug access ports and methods of fabricating the same

#23 | 2017-03-30
US20170092602A1
Electricity

Packaged integrated circuit device with cantilever structure

#24 | 2017-03-23
US20170084573A1
Electricity

Microelectronic package debug access ports

#25 | 2017-01-26
US20170025400A1
Electricity

System-in-package logic and method to control an external packaged memory device

InventorID:

1781807 ⎘