Inventor profile of:

Kumar Ganapathy

City:

Los Altos, California

Country:

United States

Published Applications:

51

Last publication date:

2018-05-03

Top Assignees for applications by Kumar Ganapathy

The entities that hold a legal rights for patent applications filed by inventor Ganapathy Kumar:

Recent patent applications by Ganapathy Kumar

Kumar Ganapathy from Los Altos, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-05-03
US20180121379A9
Physics

READ WRITEABLE RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY MODULES

#2 | 2017-08-03
US20170220461A1
Physics

Apparatus with a memory controller configured to control access to randomly accessible non-volatile memory

#3 | 2016-11-24
US20160342195A1
Physics

Network computer systems with power management

#4 | 2016-04-28
US20160117258A1
Physics

Seamless application access to hybrid main memory

#5 | 2016-04-28
US20160117131A1
Physics

Asymmetric memory migration in hybrid main memory

#6 | 2016-03-31
US20160092384A1
Physics

Read writeable randomly accessible non-volatile memory modules

#7 | 2015-11-19
US20150332768A1
Physics

Memory modules with multi-chip packaged integrated circuits having flash memory

#8 | 2015-01-29
US20150032940A1
Physics

Methods of managing power in network computer systems

#9 | 2015-01-08
US20150012721A1
Physics

Seamless application access to hybrid main memory

#10 | 2014-12-25
US20140379969A1
Physics

Memory channel connected non-volatile memory

#11 | 2014-09-11
US20140258653A1
Physics

Integrating data from symmetric and asymmetric memory

#12 | 2014-09-11
US20140258603A1
Physics

Asymmetric memory migration in hybrid main memory

#13 | 2014-06-03
US12490930
Physics

Methods for a random read and read/write block accessible memory

#14 | 2014-03-13
US20140075106A1
Physics

Methods of communicating to different types of memory modules in a memory channel

#15 | 2014-03-13
US20140075101A1
Physics

Methods for accessing memory in a two-dimensional main memory having a plurality of memory slices

#16 | 2014-03-13
US20140074880A1
Physics

METHODS OF A SERVER WITH A TWO-DIMENSIONAL MAIN MEMORY

#17 | 2014-03-13
US20140071755A1
Physics

Multi-chip packaged integrated circuit with flash memory and slave memory controller

#18 | 2013-08-27
US12490941
-

Network computing systems having shared memory clouds with addresses of disk-read-only memories mapped into processor address spaces

#19 | 2013-05-30
US20130138877A1
Physics

Method and apparatus for distributed direct memory access for systems on chip

#20 | 2013-05-30
US20130138874A1
Physics

Systems with programmable heterogeneous memory controllers for main memory

#21 | 2013-05-30
US20130138872A1
Physics

Apparatus with a memory controller configured to control access to randomly accessible non-volatile memory

#22 | 2013-05-30
US20130138844A1
Physics

Non-volatile type memory modules for main memory

#23 | 2013-04-09
US12490914
-

Random read and read/write block accessible memory

#24 | 2013-01-03
US20130007338A1
Physics

Handling writes to a memory including asymmetric and symmetric components

#25 | 2012-10-11
US20120260030A1
Physics

Seamless application access to hybrid main memory

#26 | 2012-08-02
US20120198141A1
Physics

Integrating data from symmetric and asymmetric memory

#27 | 2012-08-02
US20120198140A1
Physics

Asymmetric memory migration in hybrid main memory

#28 | 2012-03-29
US20120079181A1
Physics

Translating memory modules for main memory

#29 | 2011-07-14
US20110173371A1
Physics

Writing to asymmetric memory

#30 | 2011-07-07
US20110167205A1
Physics

Seamless application access to hybrid main memory

#31 | 2011-01-27
US20110022788A1
Physics

Integrating data from symmetric and asymmetric memory

#32 | 2010-12-23
US20100325383A1
Physics

Asymmetric memory migration in hybrid main memory

#33 | 2010-10-28
US20100274959A1
Physics

Methods for main memory with non-volatile type memory modules

#34 | 2010-10-28
US20100274958A1
Physics

Methods of assembly of a computer system with randomly accessible non-volatile memory

#35 | 2010-10-28
US20100274957A1
Physics

System and apparatus with a memory controller configured to control access to randomly accessible non-volatile memory

#36 | 2010-10-28
US20100274956A1
Physics

Systems and apparatus for main memory

#37 | 2009-10-08
US20090254689A1
Physics

Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers

#38 | 2009-08-20
US20090210636A1
Physics

Systems for two-dimensional main memory including memory modules with read-writeable non-volatile memory devices

#39 | 2009-08-20
US20090210616A1
Physics

Memory modules for two-dimensional main memory

#40 | 2008-07-24
US20080177978A1
Physics

Integrating data from symmetric and asymmetric memory

#41 | 2008-05-08
US20080109629A1
Physics

Asymmetric memory migration in hybrid main memory

#42 | 2008-05-08
US20080109593A1
Physics

Writing to asymmetric memory

#43 | 2008-05-08
US20080109592A1
Physics

Seamless application access to hybrid main memory

#44 | 2008-04-03
US20080082766A1
Physics

Systems and apparatus with programmable memory control for heterogeneous main memory

#45 | 2008-04-03
US20080082751A1
Physics

Programmable heterogeneous memory controllers for main memory with different memory modules

#46 | 2008-04-03
US20080082750A1
Physics

METHODS OF COMMUNICATING TO, MEMORY MODULES IN A MEMORY CHANNEL

#47 | 2008-04-03
US20080082734A1
Physics

Methods for main memory in a system with a memory controller configured to control access to non-volatile memory, and related technologies

#48 | 2008-04-03
US20080082733A1
Physics

Methods for main memory with non-volatile type memory modules, and related technologies

#49 | 2008-04-03
US20080082732A1
Physics

Systems and apparatus for main memory with non-volatile type memory modules, and related technologies

#50 | 2008-04-03
US20080082731A1
Physics

Main memory in a system with a memory controller configured to control access to non-volatile memory, and related technologies

#51 | 2005-03-17
US20050060632A1
Electricity

Apparatus and methods for forward error correction decoding

InventorID:

18000 ⎘