Ossining, New York
United States
42
2025-10-16
The entities that hold a legal rights for patent applications filed by inventor Wisniewski Robert W.:
Robert W. Wisniewski from Ossining, US has applied for patents for these inventions. The list has both pending applications and granted patents:
ENTANGLED THREADS
#2 | 2016-06-23Scalable synchronization mechanism for distributed memory
#3 | 2016-05-19Method and apparatus for a hierarchical synchronization barrier in a multi-node system
#4 | 2015-05-21Location-based vehicle powertrain regulation system
#5 | 2015-01-15Providing navigational support through corrective data
#6 | 2014-12-25Creation and prioritization of multiple virtual universe teleports in response to an event
#7 | 2014-06-26Location-based vehicle powertrain regulation system
#8 | 2014-06-26Location-based vehicle powertrain regulation system
#9 | 2014-05-01Virtual meetings
#10 | 2014-05-01Virtual meetings
#11 | 2013-12-05Mechanism for optimized intra-die inter-nodelet messaging communication
#12 | 2013-11-28MEETING ATTENDANCE PLANNER
#13 | 2013-11-28MEETING ATTENDANCE PLANNER
#14 | 2013-10-03Method to utilize cores in different operating system partitions
#15 | 2013-10-03Method to embed a light-weight kernel in a full-weight kernel to provide a heterogeneous execution environment
#16 | 2013-01-10Method and apparatus for a hierarchical synchronization barrier in a multi-node system
#17 | 2013-01-03Mechanisms for efficient intra-die/intra-chip collective messaging
#18 | 2012-08-09Method for guaranteeing program correctness using fine-grained hardware speculative execution
#19 | 2012-08-02Using DMA for copying performance counter data to memory
#20 | 2012-07-19LOCAL-ONLY SYNCHRONIZING OPERATIONS
#21 | 2012-07-12METHOD AND APPARATUS FOR A HIERARCHICAL SYNCHRONIZATION BARRIER IN A MULTI-NODE SYSTEM
#22 | 2012-07-12Mechanisms for efficient intra-die/intra-chip collective messaging
#23 | 2012-05-17LOCAL SYNCHRONIZATION IN A MEMORY HIERARCHY
#24 | 2012-03-15Memory architecture with policy based data storage
#25 | 2012-01-26Memory page management in a tiered memory system
#26 | 2011-10-06Message passing with queues and channels
#27 | 2011-06-30Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller
#28 | 2011-05-26Scheduling threads having complementary functional unit usage on SMT processors
#29 | 2010-11-04Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements
#30 | 2010-09-30Prefetch engine based translation prefetching
#31 | 2009-07-09Latency-aware thread scheduling in non-uniform cache architecture systems
#32 | 2008-11-20METHOD AND SYSTEM FOR OPTIMIZING COMMUNICATION IN MPI PROGRAMS FOR AN EXECUTION ENVIRONMENT
#33 | 2008-10-23Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint
#34 | 2008-09-18Quality of service scheduling for simultaneous multi-threaded processors
#35 | 2008-07-10Architecture support of memory access coloring
#36 | 2008-07-10Cache coherence monitoring and feedback
#37 | 2008-07-10Color-based cache monitoring
#38 | 2008-02-07Methods and arrangements for detecting and managing viewability of screens, windows and like media
#39 | 2008-01-24Quality of service scheduling for simultaneous multi-threaded processors
#40 | 2008-01-24Operating system thread scheduling for optimal heat dissipation
#41 | 2008-01-10Mechanism to save and restore cache and translation trace for fast context switch
#42 | 2008-01-10Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
18094 ⎘