Haifa
Israel
195
2026-03-12
The entities that hold a legal rights for patent applications filed by inventor Weissmann Eliezer:
Eliezer Weissmann from Haifa, IL has applied for patents for these inventions. The list has both pending applications and granted patents:
APPLICATION PRIORITY BASED POWER MANAGEMENT FOR A COMPUTER DEVICE
#2 | 2025-10-02COHERENT CACHE FABRIC WITH REDUCED POWER MODE
#3 | 2025-02-20PROCESSOR SYSTEM POWER AND PERFORMANCE MANAGEMENT
#4 | 2025-01-02SYSTEM, METHOD AND APPARATUS FOR HARDWARE-BASED CORE PARKING USING WORKLOAD TELEMETRY INFORMATION
#5 | 2024-07-25APPARATUSES, METHODS, AND SYSTEMS FOR HARDWARE CONTROL OF PROCESSOR PERFORMANCE LEVELS
#6 | 2024-07-25APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR CORE
#7 | 2024-07-11APPLICATION PRIORITY BASED POWER MANAGEMENT FOR A COMPUTER DEVICE
#8 | 2024-04-25APPLICATION PRIORITY BASED POWER MANAGEMENT FOR A COMPUTER DEVICE
#9 | 2023-12-07System, apparatus and method for loose lock-step redundancy power management
#10 | 2023-08-31Apparatuses, methods, and systems for instructions to request a history reset of a processor core
#11 | 2023-06-01Processor Having Accelerated User Responsiveness In Constrained Environment
#12 | 2023-03-09Apparatuses, methods, and systems for instructions to request a history reset of a processor core
#13 | 2023-03-02MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL
#14 | 2023-01-19DEVICE, METHOD AND SYSTEM TO PROVIDE THREAD SCHEDULING HINTS TO A SOFTWARE PROCESS
#15 | 2022-11-24Methods of hardware and software-coordinated opt-in to advanced features on hetero ISA platforms
#16 | 2022-09-08System, apparatus and method for loose lock-step redundancy power management
#17 | 2022-08-04Apparatus and method for dynamic control of microprocessor configuration
#18 | 2022-07-07Multi-level CPU high current protection
#19 | 2022-07-07System, apparatus and method for responsive autonomous hardware performance state control of a processor
#20 | 2022-06-16DYNAMIC ENERGY PERFORMANCE PREFERENCE BASED ON WORKLOADS USING AN ADAPTIVE ALGORITHM
#21 | 2022-06-09Apparatuses, methods, and systems for hardware control of processor performance levels
#22 | 2022-02-17LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES
#23 | 2021-12-30Technology for optimizing hybrid processor utilization
#24 | 2021-11-11Processor having accelerated user responsiveness in constrained environment
#25 | 2021-09-30Apparatus and method for dynamic control of microprocessor configuration
#26 | 2021-09-23DYNAMIC INTERRUPT STEERING AND PROCESSOR UNIT IDLE STATE DEMOTION
#27 | 2021-08-05Apparatuses, methods, and systems for instructions to request a history reset of a processor core
#28 | 2021-07-08System, apparatus and method for loose lock-step redundancy power management
#29 | 2021-07-01Apparatus and method for adaptively scheduling work on heterogeneous processing resources
#30 | 2021-07-01Performance monitoring in heterogeneous systems
#31 | 2021-07-01System, apparatus and method for responsive autonomous hardware performance state control of a processor
#32 | 2021-06-24Application priority based power management for a computer device
#33 | 2021-04-01Methods of hardware and software coordinated opt-in to advanced features on hetero ISA platforms
#34 | 2021-02-25Technology for dynamically grouping threads for energy efficiency
#35 | 2021-01-28Technology for managing per-core performance states
#36 | 2021-01-21Power control arbitration
#37 | 2020-09-10Multi-level loops for computer processor control
#38 | 2020-09-03Utilization metrics for processing engines
#39 | 2020-08-27Thread Scheduling Using Processing Engine Information
#40 | 2020-07-09MECHANISM FOR ISSUING REQUESTS TO AN ACCELERATOR FROM MULTIPLE THREADS
#41 | 2020-07-02Controlling power state demotion in a processor
#42 | 2020-04-23Modifying processor frequency based on interrupt rate
#43 | 2020-04-23System and method for communication using a register management array circuit
#44 | 2020-02-20System, apparatus and method for loose lock-step redundancy power management
#45 | 2020-02-20System, apparatus and method for loose lock-step redundancy power management
#46 | 2020-01-09System, apparatus and method for loose lock-step redundancy power management in a processor
#47 | 2019-10-17Collaborative processor and system performance and power management
#48 | 2019-08-01Processor having accelerated user responsiveness in constrained environment
#49 | 2019-08-01Dynamically controlling cache size to maximize energy efficiency
#50 | 2019-07-11Enabling a non-core domain to control memory bandwidth in a processor
#51 | 2019-07-04PROCESSOR, METHOD, AND SYSTEM FOR REDUCING LATENCY IN ACCESSING REMOTE REGISTERS
#52 | 2019-07-04System, apparatus and method for controlling a processor based on effective stress information
#53 | 2019-06-27System, apparatus and method for processor-external override of hardware performance state control of a processor
#54 | 2019-05-23Mechanism for saving and retrieving micro-architecture context
#55 | 2019-05-23Multi-level loops for computer processor control
#56 | 2019-04-25Dynamically controlling cache size to maximize energy efficiency
#57 | 2019-04-25Dynamically controlling cache size to maximize energy efficiency
#58 | 2019-04-04Utilization Metrics for Processing Engines
#59 | 2019-04-04Dynamic performance biasing in a processor
#60 | 2019-04-04THREAD SCHEDULING USING PROCESSING ENGINE INFORMATION
#61 | 2019-04-04Thread scheduling using processing engine information
#62 | 2019-02-07System, Apparatus And Method For Data Driven Low Power State Control Based On Performance Monitoring Information
#63 | 2019-02-07System, apparatus and method for responsive autonomous hardware performance state control of a processor
#64 | 2019-01-10Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency
#65 | 2019-01-10Dynamically Controlling Cache Size To Maximize Energy Efficiency
#66 | 2019-01-03System, apparatus and method for loose lock-step redundancy power management
#67 | 2018-12-20DYNAMIC OFFLINING AND ONLINING OF PROCESSOR CORES
#68 | 2018-11-22System, Apparatus And Method For Performing In-Field Self-Testing Of A Processor
#69 | 2018-11-01MODIFYING AN OPERATING FREQUENCY IN A PROCESSOR
#70 | 2018-08-16Apparatuses, methods, and systems for hardware control of processor performance levels
#71 | 2018-05-03Forcing a processor into a low power state
#72 | 2018-04-05Multi-level loops for computer processor control
#73 | 2018-04-05System and method for communication using a register management array circuit
#74 | 2018-03-01Linear to physical address translation with support for page attributes
#75 | 2018-03-01Controlling a performance state of a processor using a combination of package and thread hint information
#76 | 2018-03-01Method for booting a heterogeneous system and presenting a symmetric core view
#77 | 2018-02-08Providing an interface for demotion control information in a processor
#78 | 2017-12-28Processor having accelerated user responsiveness in constrained environment
#79 | 2017-12-28Controlling performance states of processing engines of a processor
#80 | 2017-12-28Controlling forced idle state operation in a processor
#81 | 2017-10-26Multi-level CPU high current protection
#82 | 2017-06-22Method and apparatus for providing power state information using in-band signaling
#83 | 2017-06-01Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#84 | 2017-05-25Enhancing power-performance efficiency in a computer system when bursts of activity occurs when operating in low power
#85 | 2017-05-11Dynamically updating at least one power management operational parameter pertaining to a turbo mode of a processor for increased performance
#86 | 2017-04-20APPARATUS AND METHOD FOR ACCELERATING OPERATIONS IN A PROCESSOR WHICH USES SHARED VIRTUAL MEMORY
#87 | 2017-04-20Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#88 | 2017-04-06Enabling a non-core domain to control memory bandwidth in a processor
#89 | 2017-03-30Techniques for flexible and dynamic frequency-related telemetry
#90 | 2017-03-23User level control of power management policies
#91 | 2017-01-26Extension of CPU context-state management for micro-architecture state
#92 | 2017-01-19Apparatus and method for low-latency invocation of accelerators
#93 | 2017-01-19Apparatus and method for low-latency invocation of accelerators
#94 | 2017-01-12Dynamically controlling cache size to maximize energy efficiency
#95 | 2017-01-05Collaborative processor and system performance and power management
#96 | 2016-12-01Controlling performance states of processing engines of a processor
#97 | 2016-11-17Apparatus and method for accelerating operations in a processor which uses shared virtual memory
#98 | 2016-11-10Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator
#99 | 2016-10-27Enabling a non-core domain to control memory bandwidth in a processor
#100 | 2016-09-08Mapping a performance request to an operating frequency in a processor
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