Boris A. Babayan

Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator

Apparatus and methods to support counted loop exits in a multi-strand loop processor

APPARATUS AND METHODS OF DECOMPOSING LOOPS TO IMPROVE PERFORMANCE AND POWER EFFICIENCY

Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor

Method to do control speculation on loads in a high performance strand-based loop accelerator

Method and Apparatus for Scheduling of Instructions in a Multi-Strand Out-Of-Order Processor

HARDWARE-ASSISTED SOFTWARE VERIFICATION AND SECURE EXECUTION

Hardware apparatuses and methods to control access to a multiple bank data cache

Instruction and logic for sorting and retiring stores

PROCESSOR LOGIC AND METHOD FOR DISPATCHING INSTRUCTIONS FROM MULTIPLE STRANDS

Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor

INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE

Hardware apparatuses and methods to control access to a multiple bank data cache

Instructions for manipulating a multi-bit predicate register for predicating instruction sequences

INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR

Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor

Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor

Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits