Inventor profile of:

Erwin E. Yu

City:

San Jose, California

Country:

United States

Published Applications:

27

Last publication date:

2026-02-05

Top Assignees for applications by Erwin E. Yu

The entities that hold a legal rights for patent applications filed by inventor Yu Erwin E.:

Recent patent applications by Yu Erwin E.

Erwin E. Yu from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-02-05
US20260038589A1
Physics

SINGLE COMMAND SHADOW PROGRAMMING

#2 | 2025-12-18
US20250384907A1
Physics

BIAS CURRENT GENERATION METHODS AND SYSTEMS FOR FAST CURRENT SENSING

#3 | 2025-03-20
US20250098159A1
Electricity

MEMORY DEVICES INCLUDING PAD STRUCTURES

#4 | 2025-01-02
US20250008727A1
Electricity

MEMORY DEVICES AND ELECTRONIC SYSTEMS

#5 | 2024-12-26
US20240428862A1
Physics

SEEDING BIAS CONTROL FOR SUB-BLOCK GROUPS IN A MEMORY DEVICE

#6 | 2024-06-20
US20240203508A1
Physics

SELECTIVE MANAGEMENT OF ERASE OPERATIONS IN MEMORY DEVICES THAT ENABLE SUSPEND COMMANDS

#7 | 2024-05-23
US20240170075A1
Physics

MANAGING SENSE AMPLIFIER LATCH AND DATA LATCH VOLTAGE TO REDUCE STANDBY CURRENT

#8 | 2023-11-09
US20230360709A1
Physics

Managing sub-block erase operations in a memory sub-system

#9 | 2023-06-01
US20230170016A1
Physics

Memory array structures and methods of forming memory array structures

#10 | 2023-05-25
US20230162793A1
Physics

Memory devices with four data line bias levels

#11 | 2023-03-16
US20230078401A1
Physics

Managing programming convergence associated with memory cells of a memory sub-system

#12 | 2023-03-02
US20230066649A1
Electricity

Microelectronic devices, and related memory devices and electronic systems

#13 | 2023-03-02
US20230063656A1
Physics

Selective management of erase operations in memory devices that enable suspend commands

#14 | 2023-02-16
US20230047662A1
Electricity

Microelectronic devices, and related memory devices and electronic systems

#15 | 2023-02-09
US20230039026A1
Physics

Memory devices with four data line bias levels

#16 | 2022-12-22
US20220404408A1
Physics

Apparatus for determination of capacitive and resistive characteristics of access lines

#17 | 2022-09-01
US20220277795A1
Physics

Managing sub-block erase operations in a memory sub-system

#18 | 2022-06-30
US20220208278A1
Physics

Sense circuit to sense two states of a memory cell

#19 | 2022-06-09
US20220180952A1
Physics

Managing programming convergence associated with memory cells of a memory sub-system

#20 | 2021-07-01
US20210202009A1
Physics

Managing sub-block erase operations in a memory sub-system

#21 | 2021-07-01
US20210201993A1
Physics

Memory array structures and methods for determination of resistive characteristics of access lines

#22 | 2021-07-01
US20210199703A1
Physics

Apparatus and methods for determination of capacitive and resistive characteristics of access lines

#23 | 2018-12-25
US15721774
Physics

Sense matching for hard and soft memory reads

#24 | 2017-03-23
US20170084347A1
Physics

On demand knockout of coarse sensing based on dynamic source bounce detection

#25 | 2011-09-29
US20110235429A1
Physics

Method and apparatus for programming flash memory

#26 | 2010-05-06
US20100110797A1
Physics

Method and apparatus for programming flash memory

#27 | 2007-11-15
US20070263449A1
Physics

Method and apparatus for programming flash memory

InventorID:

1832546 ⎘