Inventor profile of:

Pankaj Kumar

City:

Chandler, Arizona

Country:

United States

Published Applications:

29

Last publication date:

2024-11-14

Top Assignees for applications by Pankaj Kumar

The entities that hold a legal rights for patent applications filed by inventor Kumar Pankaj:

Recent patent applications by Kumar Pankaj

Pankaj Kumar from Chandler, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-11-14
US20240378160A1
Physics

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

#2 | 2023-06-15
US20230185747A1
Physics

Presentation of direct accessed storage under a logical drive model

#3 | 2020-11-05
US20200349100A1
Physics

Presentation of direct accessed storage under a logical drive model

#4 | 2019-06-13
US20190179786A1
Physics

Hardware-based virtual machine communication supporting direct memory access data transfer

#5 | 2019-05-16
US20190147938A1
Physics

Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode

#6 | 2019-02-28
US20190065415A1
Physics

TECHNOLOGIES FOR LOCAL DISAGGREGATION OF MEMORY

#7 | 2019-02-07
US20190045668A1
Electricity

Technologies for improving processor thermal design power

#8 | 2018-12-06
US20180352679A1
Electricity

MEMORY DEVICE CARRIER FOR HIGH DENSITY FRONT SERVICEABLE RACK DRIVE CHASSIS

#9 | 2018-11-01
US20180314319A1
Physics

Providing per core voltage and frequency control

#10 | 2018-08-09
US20180225237A1
Physics

Hardware-based virtual machine communication

#11 | 2017-10-05
US20170286349A1
Physics

Method, apparatus, and system for plugin mechanism of computer extension bus

#12 | 2017-02-09
US20170040051A1
Physics

Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode

#13 | 2016-11-17
US20160335208A1
Physics

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

#14 | 2016-10-27
US20160313785A1
Physics

Providing per core voltage and frequency control

#15 | 2016-04-14
US20160103474A1
Physics

Providing per core voltage and frequency control

#16 | 2016-04-07
US20160098079A1
Physics

Providing per core voltage and frequency control

#17 | 2016-04-07
US20160098078A1
Physics

Providing per core voltage and frequency control

#18 | 2016-03-31
US20160092123A1
Physics

MEMORY WRITE MANAGEMENT IN A COMPUTER SYSTEM

#19 | 2016-03-31
US20160092118A1
Physics

MEMORY WRITE MANAGEMENT IN A COMPUTER SYSTEM

#20 | 2015-05-21
US20150143139A1
Physics

Providing per core voltage and frequency control

#21 | 2014-07-03
US20140189212A1
Physics

Presentation of direct accessed storage under a logical drive model

#22 | 2014-03-20
US20140082451A1
Physics

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

#23 | 2013-07-18
US20130185570A1
Physics

Providing per core voltage and frequency control

#24 | 2013-01-03
US20130007573A1
Physics

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

#25 | 2012-06-28
US20120166909A1
Physics

Method and apparatus for increasing data reliability for raid operations

#26 | 2012-03-29
US20120079290A1
Physics

Providing per core voltage and frequency control

#27 | 2011-09-29
US20110238909A1
Physics

Multicasting Write Requests To Multiple Storage Controllers

#28 | 2011-06-02
US20110131373A1
Physics

Mirroring data between redundant storage controllers of a storage system

#29 | 2010-12-30
US20100332756A1
Physics

Processing out of order transactions for mirrored subsystems using a cache to track write operations

InventorID:

18548 ⎘