Thomas Wagner

ASSEMBLY OF 2XD MODULE USING HIGH DENSITY INTERCONNECT BRIDGES

BARE-DIE SMART BRIDGE CONNECTED WITH COPPER PILLARS FOR SYSTEM-IN-PACKAGE APPARATUS

FAN OUT PACKAGE WITH INTEGRATED PERIPHERAL DEVICES AND METHODS

BARE-DIE SMART BRIDGE CONNECTED WITH COPPER PILLARS FOR SYSTEM-IN-PACKAGE APPARATUS

BARE-DIE SMART BRIDGE CONNECTED WITH COPPER PILLARS FOR SYSTEM-IN-PACKAGE APPARATUS

SUPPORT STRUCTURES FOR SEMICONDUCTOR SUBSTRATES

ASSEMBLY AND METHOD FOR PREVENTING WARPAGE IN A SEMICONDUCTOR PACKAGE

THERMAL INTERFACE MATERIAL ON A SURFACE OF A DIE IN A CAVITY

DIRECT DIE-TWO-DIE CONNECTION THROUGH AN INTERPOSER WITHOUT VIAS

VIAS THROUGH A DIE THAT ARE ELECTRICALLY ISOLATED FROM ACTIVE CIRCUITRY IN THE DIE

Routing and Passive Components in a Direct Bonding Layer

GLASS LAYERS AND CAPACITORS FOR USE WITH INTEGRATED CIRCUIT PACKAGES

DIELECTRIC MATERIAL AND A MOLD COMPOUND WITH DIFFERENT DIELECTRIC CONSTANTS COUPLED TO A DIE THAT INCLUDES INTEGRATED CIRCUITRY

ANTENNA MODULES AND COMMUNICATION DEVICES

SPHERICAL ANTENNA ARRANGEMENT WITH Z-DIMENSIONAL PLATED ANTENNA STRUCTURES

MILLIMETER WAVE ANTENNA ESD PROTECTION USING INTEGRATED POLYMER NANOCOMPOSITE DEVICES

ANTENNA MODULE WITH CAPACITIVE COUPLING

RF ANTENNA MODULE USING COPPER-TO-COPPER INTERCONNECTS BETWEEN THE ANTENNA AND THE RF DIE

INTEGRATED MILLIMETER WAVE ANTENNA ESD PROTECTION

PACKAGE FORMATION METHODS INCLUDING COUPLING A MOLDED ROUTING LAYER TO AN INTEGRATED ROUTING LAYER

FAN OUT PACKAGE WITH INTEGRATED PERIPHERAL DEVICES AND METHODS

ASSEMBLY OF 2XD MODULE USING HIGH DENSITY INTERCONNECT BRIDGES

INTEGRATING AND ACCESSING PASSIVE COMPONENTS IN WAFER-LEVEL PACKAGES

CHIP-FIRST LAYERED PACKAGING ARCHITECTURE

THREE-DIMENSIONAL STACK COOLING WINGS

HETEROGENEOUS PACKAGES HAVING THERMAL TOWERS

INTEGRATED CIRCUIT PACKAGES HAVING REDUCED Z-HEIGHT AND HEAT PATH

GROOVED PACKAGE

INTEGRATED CIRCUIT PACKAGES HAVING REDUCED Z-HEIGHT

MICROELECTRONIC ASSEMBLIES INCLUDING STIFFENERS AROUND INDIVIDUAL DIES

STACKED DIE PACKAGING ARCHITECTURE WITH CONDUCTIVE VIAS ON INTERPOSER

PACKAGING ARCHITECTURE WITH REINFORCEMENT STRUCTURE IN PACKAGE SUBSTRATE

PACKAGING ARCHITECTURE WITH REINFORCEMENT STRUCTURE IN PACKAGE SUBSTRATE

Integrating and accessing passive components in wafer-level packages

TRANSFORMERS BASED ON BURIED POWER RAIL TECHNOLOGY

BURIED POWER RAILS INTEGRATED WITH DECOUPLING CAPACITANCE

Semiconductor Die, Heat Spreader, Semiconductor Package, Semiconductor Device, and Methods

Semiconductor Structure and Method for Forming a Semiconductor Structure

SIGNAL ROUTING USING STRUCTURES BASED ON BURIED POWER RAILS

Semiconductor Die, Semiconductor Device and Method for Forming a Semiconductor Die

Back Side Power Supply for Electronic Devices

Package formation methods including coupling a molded routing layer to an integrated routing layer

Fan out package with integrated peripheral devices and methods

PATCH ANTENNAS STITCHED TO SYSTEMS IN PACKAGES AND METHODS OF ASSEMBLING SAME

BARE-DIE SMART BRIDGE CONNECTED WITH COPPER PILLARS FOR SYSTEM-IN-PACKAGE APPARATUS

Assembly of 2XD module using high density interconnect bridges

BARE-DIE SMART BRIDGE CONNECTED WITH COPPER PILLARS FOR SYSTEM-IN-PACKAGE APPARATUS

FACE-UP FAN-OUT ELECTRONIC PACKAGE WITH PASSIVE COMPONENTS USING A SUPPORT

WLCSP reliability improvement for package edges including package shielding

Integrating and accessing passive components in wafer-level packages

EMBEDDED-BRIDGE SUBSTRATE CONNECTORS AND METHODS OF ASSEMBLING SAME

Fan out package with integrated peripheral devices and methods

Fan out package and methods

Semiconductor packages, and methods for forming semiconductor packages

Semiconductor inductors

Patch antennas stitched to systems in packages and methods of assembling same

Vertical and lateral interconnects between dies

Face-up fan-out electronic package with passive components using a support

COMPONENT TERMINATIONS FOR SEMICONDUCTOR PACKAGES

PACKAGE DEVICES HAVING A BALL GRID ARRAY WITH SIDE WALL CONTACT PADS

Interconnect structure for stacked die in a microelectronic device

Chip scale thin 3D die stacked package

THROUGH-SILICON VIA PILLARS FOR CONNECTING DICE AND METHODS OF ASSEMBLING SAME

PACKAGES OF STACKING INTEGRATED CIRCUITS

Molded substrate package in fan-out wafer level package

Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory

Fan out package with integrated peripheral devices and methods

Bare-die smart bridge connected with copper pillars for system-in-package apparatus

Systems, methods, and apparatuses for implementing reduced height semiconductor packages for mobile electronics

Molded substrate package in fan-out wafer level package

Face-up fan-out electronic package with passive components using a support

Package including an integrated routing layer and a molded routing layer

OPTICAL FIBER CONNECTION ON PACKAGE EDGE

ELECTRONIC COMPONENT ALIGNMENT DEVICE AND METHOD

Semiconductor package having a variable redistribution layer thickness

Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory

Cross-connected multi-chip modules coupled by silicon bent-bridge interconnects and methods of assembling same

Vertical wire connections for integrated circuit package

System-in-package devices and methods for forming system-in-package devices

Electrical device and a method for forming an electrical device

FILLER INTERFACE HEAT TRANSFER SYSTEM AND DEVICES AND METHODS FOR SAME

Embedded-bridge substrate connectors and methods of assembling same

Bent-bridge semiconductive apparatus

Multi-layer redistribution layer for wafer-level packaging

Interconnect structure for a microelectronic device

Microelectronic package with illuminated backside exterior

Semiconductor package having a variable redistribution layer thickness