Chandra Mohan JHA

SEMICONDUCTOR DEVICE STACK-UP WITH BULK SUBSTRATE MATERIAL TO MITIGATE HOT SPOTS

MICROELECTRONIC PACKAGE WITH SOLDER ARRAY THERMAL INTERFACE MATERIAL (SA-TIM)

SEMICONDUCTOR DEVICE STACK-UP WITH BULK SUBSTRATE MATERIAL TO MITIGATE HOT SPOTS

Microelectronic package with solder array thermal interface material (SA-TIM)

Semiconductor device stack-up with bulk substrate material to mitigate hot spots

INTEGRATED CIRCUIT PACKAGE WITH FLIPPED HIGH BANDWIDTH MEMORY DEVICE

Thermally enhanced silicon back end layers for improved thermal performance

MODULAR TECHNIQUE FOR DIE-LEVEL LIQUID COOLING

Heatsink cutout and insulating through silicon vias to cut thermal cross-talk

Package wrap-around heat spreader

3D buildup of thermally conductive layers to resolve die height differences

Solid state thermoelectric cooler in silicon backend layers for fast cooling in turbo scenarios

Hybrid interposer of glass and silicon to reduce thermal crosstalk

Backside metallization (BSM) on stacked die packages and external silicon at wafer level, singulated die level, or stacked dies level

LATERAL HEAT REMOVAL FOR 3D STACK THERMAL MANAGEMENT

Semiconductor device stack-up with bulk substrate material to mitigate hot spots

Microelectronic package with solder array thermal interface material (SA-TIM)

Vented lids for integrated circuit packages

Microelectronic assemblies having a cooling channel

Integrated heat spreader with multiple channels for multichip packages

Sloped metal features for cooling hotspots in stacked-die packages

Using a thermoelectric cooler to reduce heat transfer between heat-conducting plates

Thermal assemblies for multi-chip packages

THERMOELECTRIC COOLER HAVING A SOLDERLESS ELECTRODE