Hsinchu
Taiwan
74
2026-05-28
The entities that hold a legal rights for patent applications filed by inventor WANG Mill-Jer:
Mill-Jer WANG from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:
CONTACTLESS ELECTRICAL INSPECTION PROCESS
#2 | 2025-11-27INSPECTION APPARATUS AND METHOD
#3 | 2025-11-06SEMICONDUCTOR DEVICE AND METHOD
#4 | 2025-02-20PACKAGE STRUCTURE, SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME
#5 | 2024-12-12Semiconductor Device and Method
#6 | 2024-11-14ANTENNA TESTING DEVICE FOR HIGH FREQUENCY ANTENNAS
#7 | 2024-09-12PROBE HEAD STRUCTURE
#8 | 2024-04-25TESTING MODULE AND TESTING METHOD USING THE SAME
#9 | 2024-03-14Semiconductor structure and manufacturing method thereof
#10 | 2024-01-25INSPECTION APPARATUS AND METHOD
#11 | 2023-10-19Antenna testing device for high frequency antennas
#12 | 2023-08-10Semiconductor device structure with magnetic element
#13 | 2023-06-01Testing module and testing method using the same
#14 | 2023-03-02Method for forming probe head structure
#15 | 2022-12-01Testing module and testing method using the same
#16 | 2022-11-10Test circuit and method
#17 | 2022-09-08Testing holders for chip unit and die package
#18 | 2022-08-25Semiconductor structure and manufacturing method thereof
#19 | 2021-12-30Antenna testing device and method for high frequency antennas
#20 | 2021-09-09Semiconductor device structure with magnetic element
#21 | 2021-04-01System and method for semiconductor device testing
#22 | 2021-03-18Electromagnetic shielding during wafer stage testing
#23 | 2021-03-04Testing module and testing method using the same
#24 | 2021-02-25Semiconductor device structure with magnetic element in testing region
#25 | 2020-12-03Test probing structure
#26 | 2020-11-12Semiconductor structure and manufacturing method thereof
#27 | 2020-11-12Test circuit and method
#28 | 2020-11-05Devices for high-density probing techniques and method of implementing the same
#29 | 2020-10-15Testing holders for chip unit and die package
#30 | 2020-08-20Alignment testing for tiered semiconductor structure
#31 | 2020-08-13Testing apparatus and testing method
#32 | 2020-07-30Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
#33 | 2019-10-03Devices for high-density probing techniques and method of implementing the same
#34 | 2019-08-08Probe head structure of probe card and testing method
#35 | 2019-04-04Testing apparatus and testing method
#36 | 2019-01-24Alignment testing for tiered semiconductor structure
#37 | 2018-12-27Testing holders for chip unit and die package
#38 | 2018-07-19Semiconductor structure and manufacturing method thereof
#39 | 2018-06-14Test circuit and method
#40 | 2018-06-14Universal test mechanism for semiconductor device
#41 | 2018-05-31Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
#42 | 2018-02-08Test probing structure
#43 | 2018-01-02Semiconductor device, test system and method of the same
#44 | 2017-09-07Alignment testing for tiered semiconductor structure
#45 | 2017-08-31Testing holders for chip unit and die package
#46 | 2017-06-01Semiconductor device and manufacturing method thereof
#47 | 2016-12-22Testing holders for chip unit and die package
#48 | 2016-10-27Devices for high-density probing techniques and method of implementing the same
#49 | 2016-08-04Testing holders for chip unit and die package
#50 | 2016-04-21Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
#51 | 2015-08-27Test circuit and method
#52 | 2015-08-27Test circuit and method
#53 | 2015-07-16Integrated fan-out wafer architecture and test method
#54 | 2015-07-02Integrated fan-out package-on-package testing
#55 | 2015-06-18Capacitance measurement circuit and method
#56 | 2015-05-14Systems for probing semiconductor wafers
#57 | 2015-04-30Structure and method for testing stacked CMOS structure
#58 | 2015-04-30Alignment testing for tiered semiconductor structure
#59 | 2014-12-04Probe card partition scheme
#60 | 2014-09-18Testing holders for chip unit and die package
#61 | 2014-09-18Test-yield improvement devices for high-density probing techniques and method of implementing the same
#62 | 2014-09-11Integrated circuit test system and method
#63 | 2014-06-19Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
#64 | 2014-02-13Three-dimensional integrated circuit and method for wireless information access thereof
#65 | 2013-08-01Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC)
#66 | 2013-06-13Test probing structure
#67 | 2013-04-25Methods for probing semiconductor wafers
#68 | 2013-04-18Probe card partition scheme
#69 | 2012-11-01Interposers of 3-dimensional integrated circuit package systems and methods of designing the same
#70 | 2012-05-31Mechanisms for resistivity measurement of bump structures
#71 | 2012-04-26Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)
#72 | 2010-11-04Method and system of testing a semiconductor device
#73 | 2010-09-16Method for assembling a wafer level test probe card
#74 | 2009-09-10Wafer level test probe card
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