Inventor profile of:

David A. Roberts

City:

Wellesley, Massachusetts

Country:

United States

Published Applications:

21

Last publication date:

2026-02-05

Top Assignees for applications by David A. Roberts

The entities that hold a legal rights for patent applications filed by inventor Roberts David A.:

Recent patent applications by Roberts David A.

David A. Roberts from Wellesley, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-02-05
US20260037189A1
Physics

DIRECT ACCESS OF A DATASET IN A FABRIC-ATTACHED MEMORY FOR A DISTRIBUTED WORKFLOW

#2 | 2026-01-29
US20260029953A1
Physics

MODIFYING MACHINE LEARNING PARAMETERS IN MEMORY SYSTEMS

#3 | 2026-01-29
US20260029952A1
Physics

GENERATING TOKENS USING NEAR-MEMORY COMPUTING

#4 | 2026-01-22
US20260023756A1
Physics

DATA GROUP SYNCHRONIZATION

#5 | 2025-03-06
US20250077411A1
Physics

MEMORY ACCESS STATISTICS MONITORING

#6 | 2024-03-14
US20240086315A1
Physics

Memory access statistics monitoring

#7 | 2023-08-03
US20230244598A1
Physics

Memory access statistics monitoring

#8 | 2022-07-21
US20220229712A1
Physics

Self-regulating power management for a neural network system

#9 | 2022-06-23
US20220199144A1
Physics

Apparatuses and methods for row hammer based cache lockdown

#10 | 2022-03-01
US17127654
Physics

Apparatuses and methods for row hammer based cache lockdown

#11 | 2020-06-04
US20200174748A1
Physics

Sorting instances of input data for processing through a neural network

#12 | 2020-03-12
US20200081864A1
Physics

Instructions for performing multi-line memory accesses

#13 | 2019-10-17
US20190317832A1
Physics

Fast thread wake-up through early lock release

#14 | 2019-10-17
US20190317831A1
Physics

Improving latency by performing early synchronization operations in between sets of program operations of a thread

#15 | 2019-08-01
US20190235940A1
Physics

Self-regulating power management for a neural network system

#16 | 2019-07-04
US20190205492A1
Physics

Input-output processing on a remote integrated circuit chip

#17 | 2019-04-04
US20190102175A1
Physics

Hybrid analog-digital floating point number representation and arithmetic

#18 | 2019-02-07
US20190042313A1
Physics

Shareable FPGA compute engine

#19 | 2018-11-22
US20180337863A1
Electricity

Modifying carrier packets based on information in tunneled packets

#20 | 2018-10-18
US20180300265A1
Physics

Resilient vertical stacked chip network for routing memory requests to a plurality of memory dies

#21 | 2017-07-27
US20170212760A1
Physics

Instruction set and micro-architecture supporting asynchronous memory access

InventorID:

1941102 ⎘