Advanced Micro Devices, Inc.

Pin Cutout in Memory Modules

DSP MEMORY MANAGEMENT FOR AUDIO STREAM OFFLOADS

NEURAL LIGHT SAMPLING

SYSTEM AND METHOD OF BUILDING BVH WITH ORIENTED BOUNDING BOXES

TECHNIQUES FOR IMPROVING COMPRESSION BY FORCING A HIT FOR BOUNDING VOLUMES OF A BVH

GRAPHICS LIBRARY EXTENSIONS

EFFICIENT PROCESSING OF OPACITY MICRO-MAPS

Bandwidth Management for Real-Time and Best-Effort Clients Under Loaded System Conditions

SMART RETIMER DEVICE

CACHE RESIDENCY CONTROL

Mixed Memory Architecture Cache Level

Stacked Die Configuration with Metadata Storage

Selective Insertion of Prefetched Data and Instructions

Last-Level-Cache-Aware Reader-Writer Semaphore

Accelerating and Improved Fairness for Semaphores

EFFICIENT RESOURCE MANAGEMENT FOR HIGHLY CONCURRENT SCALAR-VECTOR SYSTEMS

Selective Data Compression for Non-Critical Memory Requests

POWER REDUCTION FOR COMMAND SUB-QUEUE MEMORIES

Adaptive Voltage Regulator Configurations

SYSTEMS AND METHODS FOR IMPROVING UNIFORMITY OF PROCESSING DEVICE PERFORMANCE ON COMPUTING BOARDS

FASTER DECOMPRESSION BY CONSTRAINING DATA COMPRESSION

Learning Grainy Texture Parameters in the Frequency Domain

Decoding JPEG-Like Video Codecs Using a Hardware JPEG Decoder

Driver Support for ROMless Graphics Processors

REMOTE MEMORY TRAFFIC MANAGEMENT

CONFIDENTIAL COMPUTING GUEST PRIVATE PAGE

Dirty Data Tracking for Live Migration of Virtual Machines

DEVICES AND METHODS FOR DYNAMICALLY ADAPTING THERMAL CONSTRAINTS ON THE OPERATION OF COMPUTING DEVICES

ULTRASOUND ASSISTED SPATIAL AUDIO

KEYWORD-BASED DEVICE ACTIVATION TO AVOID FALSE POSITIVES

Drift-Based Margin Optimizer

In-Situ Electrical Connectivity Detection

Parallel-Split All-to-All Data Communication

Processor Frequency Control For Expected Demand

SENSOR MONITORING FOR SYSTEM DIE

DATA-PARALLEL DECOMPRESSION OF DENSE GEOMETRY FORMAT TRIANGLE MESHES

FINE-GRAINED PREEMPTION OF A DATA FLOW ARCHITECTURE BASED NEURAL PROCESSING UNIT

MULTILAYER INTERPOSER FOR THROUGH GLASS VIA

COMMAND STREAM STITCHING FOR HARDWARE ACCELERATION

HYBRID VOLTAGE REGULATOR

STACKED DIE CROSSING

Work Distribution in a Data Center based on Compute Node Efficiency

USER FEEDBACK IN MEMORY TRAINING STARTUP SEQUENCES

AI-BASED GAME AND RENDERING ENGINE

Vertical Module Connector with Pin-Clamp Mechanism

Multi-die Memory Chip with Individually Connected Data (DQ) Pins

Buffer Device for Combining and Splitting Pseudo Channel Data Strobes (DQS)

Multi-die Memory Package with Individually Accessible Command/Address Pins

Extended Length Memory System with Multiple Channels

Buffer for Error Correction in Memory Systems

SIDEBAND AUDIO OFFLOAD

PROCESSES FOR MANUFACTURING WAFER-ON-WAFER DEVICES, AND SYSTEMS INCORPORATING SUCH DEVICES

SYSTEMS AND METHODS FOR TIMER SYNCHRONIZATION

RENDERING USING MACHINE LEARNING TO GENERATE INDIRECT ILLUMINATION

DYNAMIC RAY RETURN FOR MID-TRAVERSAL AND POST-TRAVERSAL SHADING

ACCELERATING BOUNDING VOLUME HIERARCHY CONSTRUCTION WITH MACHINE LEARNING

FOLDED REGISTER FILE

Hardware Mitigation of Cache Side-Channel Attacks

PSEUDO-ACTIVE LINK STATE FOR MULTI-DIE LINK FAILURE

SYSTEMS AND METHODS FOR MIXED DIRECTORY ENTRY ORGANIZATION IN PROBE FILTER

Method and Apparatus for Efficient Memory Setting

OUT-OF-ORDER FETCH AND DECODE PIPELINES

Spatial Nonuniformity and Shading Effects Mitigation Using Machine-Learning Models

AI-BASED TECHNIQUES FOR GENERATING INTERACTIVE, ANIMATED VIDEO

INTERMEDIATE FORMATS FOR IMAGE PROCESSING PIPELINES

SYSTEMS AND METHODS FOR INTEGER-TO-FLOATING-POINT DATA TRANSFERS

CONFIDENTIAL COMPUTING OWNERSHIP CHECK

SYSTEMS AND METHODS FOR REGION-BASED PROBE FILTER SHOOTDOWN

SYSTEMS AND METHODS FOR HIGH FIDELITY REGION FROM PROBE FILTER ENTRY

PIPELINED HORIZONTAL PARALLELISM FOR LARGE LANGUAGE MODELS

OFFLOADING OPERATIONS USING A NETWORK INTERFACE CONTROLLER

SYSTEMS AND METHODS FOR ENHANCED MATRIX OPERATIONS

SYSTEMS AND METHODS FOR IMPLEMENTING AN ELECTRICAL CIRCUIT INCLUDING AN INDUCTIVE TUNING ELEMENT

Selective Encryption for Processing-in-Memory

SYSTEMS AND METHODS FOR BOOSTING A WORDLINE

SYSTEMS AND METHODS FOR LATERAL STACKING OF DIE

SYSTEMS AND METHODS FOR DATA COMMUNICATION BUS ADDRESS SHARING

Modifying System Directory Capacity based on Power State Transition

SYSTEMS AND METHODS FOR INTERPOSER SEATING INDICATION

BOUNDING VOLUME HIERARCHY CACHING BY STORING TOPOLOGY

FAST BOUNDING VOLUME HIERARCHY TREE REBUILD FOR DYNAMIC GEOMETRIES USING NEURAL NETWORKS

Isolation-Based Confidentiality

OBJECT SEARCH USING RAY TRACING HARDWARE

METHOD OF TASK TRANSITION BETWEEN HETEROGENOUS PROCESSORS

SHADOW TAG MANAGEMENT FOR ACCELERATOR PARTITIONS

SYSTEMS AND METHODS FOR MASSIVELY PARALLEL CHIP INTEGRATION

FUNCTIONAL SAFETY SYSTEM USING SAFETY CERTIFIED REAL-TIME OPERATING SYSTEM AND HYPERVISOR

Fused Data Generation and Associated Communication

SEMICONDUCTOR QUANTUM DOT

ACCELERATING NEURAL NETWORKS WITH ONE SHOT SKIP LAYER PRUNING

MEMORY CONTROLLER FOR USE WITH ROW-BUFFER MEMORY

MEMORY CONTROLLER FOR MEMORY WITH MEDIUM GRANULARITY REFRESH COMMANDS

Configurable and Scalable Power Gating and Voltage Regulation