DAVID A. BROWN

Processor core to coprocessor interface with FIFO semantics

High performance method for reduction of memory power consumption employing RAM retention mode control with low latency and maximum granularity

Tuple encoding aware direct memory access engine for scratchpad enabled multi-core processors

Database tuple-encoding-aware data partitioning in a direct memory access engine

Multicast copy ring for database direct memory access filtering engine

Row identification number generation in database direct memory access engine

Processor core to coprocessor interface with FIFO semantics

Multi-purpose events for notification and sequence control in multi-core processor systems

Run length encoding aware direct memory access filtering engine for scratchpad enabled multicore processors

Tuple encoding aware direct memory access engine for scratchpad enabled multicore processors

Data caching in a network communications processor architecture

Data caching in a network communications processor architecture

Yield-enhancing device failure analysis

Processor with configurable association between interface signal lines and clock domains

Processor with flexible clock configuration

Processor with programmable configuration of logical-to-physical address translation on a per-client basis

Function interface system and method of processing issued functions between co-processors

Fast pattern processor including a function interface system

Checksum engine and a method of operation thereof

System and method for configuring adaptive sets of links between routers in a system area network (SAN)

Multi-protocol bus system and method of operation thereof

Multi-protocol bus system and method of operation thereof

External device transmission system and a fast pattern processor employing the same

Speculative transmit for system area network latency reduction

Link extenders with error propagation and reporting