RAGHAVAN KUMAR

PRESCIENT COMPUTING

METHOD AND APPARATUS TO REDUCE REJECTION RATE OF INTEGERS GENERATED BY A RANDOM NUMBER GENERATOR

CONFIGURABLE VARIABLE-WORD SIZE XORSHIFT RANDOM NUMBER GENERATOR

Apparatus and Method for Attack-Resistant Encryption and Decryption

TECHNIQUES FOR COMPRESSED ROUTE TABLES FOR CONTENTION-FREE ROUTING ASSOCIATED WITH NUMBER-THEORETIC- TRANSFORM AND INVERSE-NUMBER-THEORETIC-TRANSFORM COMPUTATIONS

COMPUTE ENGINE CONTROL BLOCK (CCB) DISTRIBUTED DATA WORD ARCHITECTURE

TECHNIQUES FOR STALLED ROUTING ASSOCIATED WITH NUMBER-THEORETIC- TRANSFORM AND INVERSE-NUMBER-THEORETIC-TRANSFORM COMPUTATIONS

Modular Exponentiation Hardware Accelerator with Unconstrained Operands for Public Key Encryption

ON-DIE KEY GENERATOR FOR FULLY-HOMOMORPHIC ENCRYPTION RELINEARIZATION PUBLIC KEYS

UNIFIED SIDE-CHANNEL AND FAULT-INJECTION RESISTANT AES ENGINE

TECHNIQUES FOR USE OF MIXED WORD SIZE MULTIPLICATION FOR FULLY HOMOMORPHIC ENCRYPTION RELINEARIZATION

STATIC INSTRUCTION DECOUPLING (SID) FOR DATA MOVEMENT AND COMPUTE

RECONFIGURABLE COMPUTE CIRCUITRY TO PERFORM FULLY HOMOMORPHIC ENCRYPTION (FHE) TO MAP UNCONSTRAINED POWERS-OF-2 FHE POLYNOMIALS

FULLY HOMOMORPHIC ENCRYPTION

TECHNIQUES FOR TWIDDLE FACTOR GENERATION FOR NUMBER-THEORETIC-TRANSFORM AND INVERSE-NUMBER-THEORETIC-TRANSFORM COMPUTATIONS

TECHNIQUES FOR TWIDDLE FACTOR GENERATION FOR NUMBER-THEORETIC- TRANSROM AND INVERSE-NUMBER-THEORETIC-TRANFORM COMPUTATIONS

TECHNIQUES FOR CONTENTION-FREE ROUTING FOR NUMBER-THEORETIC- TRANSFORM AND INVERSE-NUMBER-THEORETIC-TRANSFORM COMPUTATIONS ROUTED THROUGH A PARALLEL PROCESSING DEVICE

ERROR DETECTION IN CRYPTOGRAPHIC SUBSTITUTION BOX OPERATIONS

SIDE-CHANNEL RESISTANT MULTIPLICATIVELY MASKED AES ENGINE WITH ZERO-VALUE ATTACK DETECTION

SIDE-CHANNEL RESISTANT BULK AES ENCRYPTION

RECONFIGURABLE SIDE-CHANNEL RESISTANT DOUBLE-THROUGHPUT AES ACCELERATOR

LSTM CIRCUIT WITH SELECTIVE INPUT COMPUTATION

COMPUTE NEAR MEMORY CONVOLUTION ACCELERATOR

PROCESSOR ARRAY FOR PROCESSING SPARSE BINARY NEURAL NETWORKS

UNIFIED ACCELERATOR FOR CLASSICAL AND POST-QUANTUM DIGITAL SIGNATURE SCHEMES IN COMPUTING ENVIRONMENTS

Secure PUF-based device authentication using adversarial challenge selection

Low latency post-quantum signature verification for fast secure-boot

Combined SHA2 and SHA3 based XMSS hardware accelerator

Time and frequency domain side-channel leakage suppression using integrated voltage regulator cascaded with runtime crypto arithmetic transformations

Odd index precomputation for authentication path computation

Accelerators for post-quantum cryptography secure hash-based signing and verification

POST QUANTUM PUBLIC KEY SIGNATURE OPERATION FOR RECONFIGURABLE CIRCUIT DEVICES

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

RECONFIGURABLE SECRET KEY SPLITTING SIDE CHANNEL ATTACK RESISTANT RSA-4K ACCELERATOR

DEVICE, SYSTEM AND METHOD FOR VERSION ROLLING WITH A BLOCKCHAIN MINING ENGINE

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Technologies for memory and I/O efficient operations on homomorphically encrypted data

Secure PUF-based device authentication using adversarial challenge selection

Programmable interface to in-memory cache processor

Device, system, and method to change a consistency of behavior by a cell circuit

Binary, ternary and bit serial compute-in-memory circuits

RANDOM-ACCESS MEMORY WITH LOADED CAPACITANCE

Deep in memory architecture using resistive switches

Self-calibrated von-neumann extractor

FinFET transistor based resistive random access memory

DIODE BASED RESISTIVE RANDOM ACCESS MEMORY

ENERGY EFFICIENT COMPUTE NEAR MEMORY BINARY NEURAL NETWORK CIRCUITS

Compute near memory convolution accelerator

Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations

Processor array for processing sparse binary neural networks

LSTM circuit with selective input computation

Post quantum public key signature operation for reconfigurable circuit devices

Unified accelerator for classical and post-quantum digital signature schemes in computing environments

Odd index precomputation for authentication path computation

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

Accelerators for post-quantum cryptography secure hash-based signing and verification

Low latency post-quantum signature verification for fast secure-boot

Combined SHA2 and SHA3 based XMSS hardware accelerator

Reconfigurable memory compression techniques for deep neural networks

Neuromorphic circuits for storing and generating connectivity information

Memory device with multiple memory arrays to facilitate in-memory computation

HOMEOSTATIC PLASTICITY CONTROL FOR SPIKING NEURAL NETWORKS

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Power side-channel attack resistant advanced encryption standard accelerator processor

Full-rail digital read compute-in-memory circuit

GLOBAL AND LOCAL TIME-STEP DETERMINATION SCHEMES FOR NEURAL NETWORKS

Binary, ternary and bit serial compute-in-memory circuits

Techniques for current-sensing circuit design for compute-in-memory

MEMORY DEVICE WITH MULTIPLE MEMORY ARRAYS TO FACILITATE IN-MEMORY COMPUTATION

Digital bit-serial multi-multiply-and-accumulate compute in memory

MEMORY DEVICE TO PROVIDE IN-MEMORY COMPUTATION FUNCTIONALITY FOR A PIPELINE CIRCUIT ARCHITECTURE

In-memory analog neural cache

Weight prefetch for in-memory neural network execution

Pipeline circuit architecture to provide in-memory computation functionality

Programmable interface to in-memory cache processor

Low synch dedicated accelerator with in-memory computation capability

In-memory multiply and accumulate with global charge-sharing

METHODOLOGY FOR PORTING AN IDEAL SOFTWARE IMPLEMENTATION OF A NEURAL NETWORK TO A COMPUTE-IN-MEMORY CIRCUIT

Compute-in-memory circuit having a multi-level read wire with isolated voltage distributions

Memoryless weight storage hardware for neural networks

Spike timing dependent plasticity in neuromorphic hardware

Reconfigurable neuro-synaptic cores for spiking neural network

Compute in memory circuits with multi-Vdd arrays and/or analog multipliers

Compute in memory circuits with time-to-digital computation

Oscillator circuitry to facilitate in-memory computation

TECHNIQUES TO POWER ENCRYPTION CIRCUITRY

Mixed-coordinate point multiplication

Multiplier circuit for accelerated square operations

Event driven and time hopping neural network

APPARATUS AND METHOD FOR CONFIGURING FAN-IN AND FAN-OUT CONNECTIONS IN A NEUROMORPHIC PROCESSOR

Neuromorphic computer with reconfigurable memory mapping for various neural network topologies

Scalable free-running neuromorphic computer

Neural network with reconfigurable sparse connectivity and online learning

Neuromorphic circuits for storing and generating connectivity information

Parallel computation techniques for accelerated cryptographic capabilities

Linear masking circuits for side-channel immunization of advanced encryption standard hardware

Programmable neuron core with on-chip learning and stochastic time step control

Power side-channel attack resistant advanced encryption standard accelerator processor

Event-driven Learning and Reward Modulation with Spike Timing Dependent Plasticity in Neuromorphic Computers

Apparatus and method for a digital neuromorphic processor