Inventor profile of:

Mark D. Smith

City:

San Jose, California

Country:

United States

Published Applications:

24

Last publication date:

2026-03-19

Top Assignees for applications by Mark D. Smith

The entities that hold a legal rights for patent applications filed by inventor Smith Mark D.:

Recent patent applications by Smith Mark D.

Mark D. Smith from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-03-19
US20260079407A1
Physics

SYSTEM AND METHOD FOR OPTIMIZING THROUGH SILICON VIA OVERLAY

#2 | 2025-08-07
US20250251669A1
Physics

SYSTEM AND METHOD FOR DETERMINING POST BONDING OVERLAY

#3 | 2025-03-27
US20250104216A1
Physics

METHOD TO CALIBRATE, PREDICT, AND CONTROL STOCHASTIC DEFECTS IN EUV LITHOGRAPHY

#4 | 2025-03-27
US20250104215A1
Physics

METHOD TO CALIBRATE, PREDICT, AND CONTROL STOCHASTIC DEFECTS IN EUV LITHOGRAPHY

#5 | 2025-03-27
US20250104214A1
Physics

METHOD TO CALIBRATE, PREDICT, AND CONTROL STOCHASTIC DEFECTS IN EUV LITHOGRAPHY

#6 | 2025-03-27
US20250103019A1
Physics

SYSTEM AND METHOD FOR MITIGATING OVERLAY DISTORTION PATTERNS CAUSED BY A WAFER BONDING TOOL

#7 | 2025-01-30
US20250035489A1
Physics

METROLOGY TARGET DESIGN FOR TILTED DEVICE DESIGNS

#8 | 2024-04-11
US20240120186A1
Electricity

PLASMA HYPERMODEL INTEGRATED WITH FEATURE-SCALE PROFILE MODEL FOR ACCELERATED ETCH PROCESS DEVELOPMENT

#9 | 2024-03-21
US20240094642A1
Physics

System and method for determining post bonding overlay

#10 | 2024-02-15
US20240053721A1
Physics

System and method for mitigating overlay distortion patterns caused by a wafer bonding tool

#11 | 2023-02-02
US20230035201A1
Physics

System and method for mitigating overlay distortion patterns caused by a wafer bonding tool

#12 | 2023-02-02
US20230032406A1
Physics

SYSTEM AND METHOD FOR DETECTING PARTICLE CONTAMINATION ON A BONDING TOOL

#13 | 2023-02-02
US20230030116A1
Physics

SYSTEM AND METHOD FOR OPTIMIZING THROUGH SILICON VIA OVERLAY

#14 | 2022-01-06
US20220005714A1
Electricity

Process-induced displacement characterization during semiconductor production

#15 | 2021-07-15
US20210216021A1
Physics

System and method for wafer-by-wafer overlay feedforward and lot-to-lot feedback control

#16 | 2019-10-31
US20190333794A1
Electricity

Process-induced displacement characterization during semiconductor production

#17 | 2018-10-09
US15289590
Physics

Systems and methods for fabricating metrology targets with sub-resolution features

#18 | 2018-09-06
US20180253016A1
Physics

Layer-to-layer feedforward overlay control with alignment corrections

#19 | 2018-07-12
US20180196358A1
Physics

Systems and methods for focus-sensitive metrology targets

#20 | 2018-06-21
US20180173839A1
Physics

Metrology recipe generation using predicted metrology images

#21 | 2018-06-07
US20180157784A1
Physics

Process compatibility improvement by fill factor modulation

#22 | 2018-04-05
US20180096906A1
Electricity

System and method for process-induced distortion prediction during wafer deposition

#23 | 2018-01-18
US20180017873A1
Physics

Method for computer modeling and simulation of negative-tone-developable photoresists

#24 | 2017-10-05
US20170287754A1
Electricity

Systems and methods for automated multi-zone detection and modeling

InventorID:

2004985 ⎘