Santa Clara, California
United States
31
2022-02-10
The entities that hold a legal rights for patent applications filed by inventor Baraskar Ashish:
Ashish Baraskar from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same
#2 | 2022-02-10Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same
#3 | 2021-12-02Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
#4 | 2021-12-02Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
#5 | 2021-12-02Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
#6 | 2021-07-01Modified verify scheme for programming a memory apparatus
#7 | 2021-06-17Three-dimensional memory device containing plural work function word lines and methods of forming the same
#8 | 2021-06-17Three-dimensional memory device containing plural work function word lines and methods of forming the same
#9 | 2021-03-18Methods for reusing substrates during manufacture of a bonded assembly including a logic die and a memory die
#10 | 2021-03-18Memory device with compensation for program speed variations due to block oxide thinning
#11 | 2020-12-10Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
#12 | 2020-12-10Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
#13 | 2020-10-22Memory device with compensation for erase speed variations due to blocking oxide layer thinning
#14 | 2020-10-01Multi-pass programming process for memory device which omits verify test in first program pass
#15 | 2020-08-20Memory device with compensation for erase speed variations due to blocking oxide layer thinning
#16 | 2020-08-13Three-dimensional memory devices using carbon-doped aluminum oxide backside blocking dielectric layer for etch resistivity enhancement and methods of making the same
#17 | 2020-07-30Memory device with compensation for program speed variations due to block oxide thinning
#18 | 2020-07-02Multi-pass programming process for memory device which omits verify test in first program pass
#19 | 2020-05-26Memory device with compensation for program speed variations due to block oxide thinning
#20 | 2018-10-30Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making thereof
#21 | 2018-10-25Reducing charge loss in data memory cell adjacent to dummy memory cell
#22 | 2018-09-04Channel pre-charge to suppress disturb of select gate transistors during erase in memory
#23 | 2018-07-10Forming memory cell film in stack opening
#24 | 2018-06-21NON-VOLATILE MEMORY WITH REDUCED VARIATIONS IN GATE RESISTANCE
#25 | 2018-05-03Non-volatile memory with reduced program speed variation
#26 | 2018-02-01NON-VOLATILE MEMORY WITH REDUCED VARIATIONS IN GATE RESISTANCE
#27 | 2018-02-01Non-Volatile Memory With Reduced Program Speed Variation
#28 | 2017-11-07Memory hole size variation in a 3D stacked memory
#29 | 2017-10-03Method of fabricating 3D NAND
#30 | 2017-08-29Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof
#31 | 2017-06-06Method of forming memory cell film
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