SanDisk Technologies LLC

Semiconductor device including fractured semiconductor dies

Memory scaling semiconductor device

Memory scaling semiconductor device

Memory scaling semiconductor device

Memory scaling semiconductor device

Persistent memory management

Memory-efficient block/object address mapping

Current distribution from different power sources

Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell

Method of making a high density slider clamp fixture

Die crack detection

Column replacement with non-dedicated replacement columns

Concurrent programming of multiple cells for non-volatile memory devices

Memory device with vpass step to reduce hot carrier injection type of program disturb

Generating random bitstreams with magnetic tunnel junctions

Asymmetric voltage ramp rate control

Duty cycle correction on an interval-by-interval basis

Ramp down sensing between program voltage and verify voltage in memory device

Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming

Ferroelectric non-volatile memory

Ferroelectric non-volatile memory

Multi-level recovery reads for memory

System and method for in-situ programming and read operation adjustments in a non-volatile memory

Adaptive programming voltage for non-volatile memory devices

Non-volatile memory with smart erase verify

Apparatus and method for reducing noise generated from locked out sense circuits in a non-volatile memory system

Resistance and gate control in decoder circuits for read and write optimization

Throughput performance for cross temperature handling scenarios

Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors

Single pulse verification of memory cells

Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors

Time sequence data management

Multi-resistance MRAM

Multi-resistance MRAM

Dynamic erase loop dependent bias voltage

Fast detection of defective memory block to prevent neighbor plane disturb

Transmission line optimization for multi-die systems

Multiple vertical TFT structures for a vertical bit line architecture

Write set operation for memory device with bit line capacitor drive

High density slider clamp fixture

Systems and methods for high-performance write operations

Non-volatile memory with fast partial page operation

Resistive memory cell programmed by metal alloy formation and method of operating thereof

Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell

Recovery of partial memory die

Multiple-mode current sources for sense operations

Vertical thin film transistors with isolation

Optimistic read operation

Three-dimensional memory device containing through-memory-level contact via structures

Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify

Reducing disturbs with delayed ramp up of selected word line voltage after pre-charge during programming

Self-aligned tubular electrode portions inside memory openings for drain select gate electrodes in a three-dimensional memory device

Three-dimensional memory device containing floating gate select transistor

Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof

Read verify for improved soft bit information for non-volatile memories with residual resistance

Partial memory die

Group read refresh

Signal path optimization for read operations in storage devices

Partial memory die with inter-plane re-mapping

Barrier modulated cell structures with intrinsic vertical bit line architecture

Methods of forming a phase change memory with vertical cross-point structure

Multi-state phase change memory device with vertical cross-point structure

Multi-state and confined phase change memory with vertical cross-point structure

Duty cycle and vox correction for complementary signals

Reducing disturbs with delayed ramp up of dummy word line after pre-charge during programming

State dependent sense circuits and pre-charge operations for storage devices

Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making the same

Output data path for non-volatile memory

Increased terrace configuration for non-volatile memory

Methods and apparatus for programming barrier modulated memory cells

Apparatus and method for identifying memory cells for data refresh based on monitor cell in a resistive memory device

Reducing hot electron injection type of read disturb in 3D memory device during signal switching transients

Non-volatile memory system with serially connected non-volatile reversible resistance-switching memory cells

Process for fabricating three dimensional non-volatile memory system

Memory cell for non-volatile memory system

Determination of fast to program word lines in non-volatile memory

Word-line pre-charging in power-on read operation to reduce programming voltage leakage

Chip with phase change memory and magnetoresistive random access memory

Duty cycle correction scheme

Reducing hot electron injection type of read disturb in 3D memory device having connected source-end select gates

On die delay range calibration

Hierarchical fail bit counting circuit in memory device

Analog-to-digital conversion with magnetic tunnel junctions

Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate

Dynamic management of programming states to improve endurance

Systems and methods for on-die control of memory command, timing, and/or control signals

Wide range zero temperature coefficient oscillators and related devices and methods

Sense circuit with two-step clock signal for consecutive sensing

State dependent sense circuits and sense operations for storage devices

Vertical selector for three-dimensional memory with planar memory cells