Inventor profile of:

Phanindra K. Mannava

City:

Folsom, California

Country:

United States

Published Applications:

25

Last publication date:

2015-07-23

Top Assignees for applications by Phanindra K. Mannava

The entities that hold a legal rights for patent applications filed by inventor Mannava Phanindra K.:

Recent patent applications by Mannava Phanindra K.

Phanindra K. Mannava from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2015-07-23
US20150207882A1
Electricity

Optimized ring protocols and techniques

#2 | 2013-10-03
US20130262781A1
Physics

Optimized ring protocols and techniques

#3 | 2013-04-25
US20130103783A1
Electricity

Reducing packet size in a communication protocol

#4 | 2012-03-29
US20120079210A1
Electricity

Optimized ring protocols and techniques

#5 | 2011-09-29
US20110238778A1
Electricity

Generating a packet including multiple operation codes

#6 | 2009-10-22
US20090265472A1
Electricity

Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components

#7 | 2009-10-06
US11525585
-

Avoiding deadlocks in a multiprocessor system

#8 | 2009-09-17
US20090235228A1
Electricity

Methodology and tools for tabled-based protocol specification and model generation

#9 | 2009-03-05
US20090064179A1
Physics

Negotiable exchange of link layer functional parameters in electronic systems having components interconnected by a point-to-point network

#10 | 2009-03-05
US20090063813A1
Physics

Method and system for flexible and negotiable exchange of link layer functional parameters

#11 | 2009-02-26
US20090055555A1
Physics

METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYER FUNCTIONAL PARAMETERS

#12 | 2008-07-03
US20080162661A1
Physics

System and method for a 3-hop cache coherency protocol

#13 | 2008-04-17
US20080091963A1
Physics

Link power saving state

#14 | 2008-04-17
US20080091825A1
Physics

Dynamic allocation of home coherency engine tracker resources in link based computing system

#15 | 2008-03-27
US20080077814A1
Physics

LINK POWER SAVING STATE

#16 | 2008-03-27
US20080075107A1
Physics

LINK POWER SAVING STATE

#17 | 2008-01-03
US20080005486A1
Physics

Coordination of snoop responses in a multi-processor system

#18 | 2007-06-07
US20070130353A1
Electricity

Link level retry scheme

#19 | 2007-04-19
US20070088863A1
Physics

System for flexible and negotiable exchange of link layer functional parameters

#20 | 2006-06-15
US20060126656A1
Electricity

Method, system, and apparatus for system level initialization

#21 | 2006-03-21
US9861260
-

Link level retry scheme

#22 | 2005-11-24
US20050262368A1
Physics

Link power saving state

#23 | 2005-09-15
US20050204193A1
Physics

Dynamic interconnect width reduction to improve interconnect availability

#24 | 2005-06-30
US20050144488A1
Physics

Method and apparatus of lowering I/O bus power consumption

#25 | 2005-01-27
US20050022100A1
Electricity

Retraining derived clock receivers

InventorID:

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