H. Peter Anvin

SYSTEM, APPARATUS AND METHODS FOR PERFORMANT READ AND WRITE OF PROCESSOR STATE INFORMATION RESPONSIVE TO LIST INSTRUCTIONS

METHOD AND APPARATUS FOR PARTIAL VIRTUALIZATION IN A PROCESSOR

FLOATING-POINT SCALAR COMPARISON WITH ENHANCED FLAGS

SOFTWARE-CONTROLLED FLAG TO REQUIRE A STACK SWITCH DURING EXECUTION

SYSTEM, APPARATUS AND METHODS FOR PERFORMANT READ AND WRITE OF PROCESSOR STATE INFORMATION RESPONSIVE TO LIST INSTRUCTIONS

FLEXIBLE RETURN AND EVENT DELIVERY

Shadow stack ISA extensions to support fast return and event delivery (FRED) architecture

Methods, apparatus, and instructions for user-level thread suspension

Shadow stack ISA extensions to support fast return and event delivery (FRED) architecture

Protecting supervisor mode information

Protecting supervisor mode information

Protecting supervisor mode information

Methods, apparatus, and instructions for user level thread suspension

Instructions and Logic to Provide Memory Access Key Protection Functionality

Protecting supervisor mode information

Avoiding premature enabling of nonmaskable interrupts when returning from exceptions

INSTRUCTIONS AND LOGIC TO PROVIDE BASE REGISTER SWAP STATUS VERIFICATION FUNCTIONALITY

Instructions and logic to provide memory access key protection functionality

Method and system for caching attribute data for matching attributes with physical addresses

Handling of binary translated self modifying code and cross modifying code

Adaptive power control

Method and system for caching attribute data for matching attributes with physical addresses

Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine

SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE

Supporting multiple byte order formats in a computer system

STORING CONTEXT INFORMATION PRIOR TO NOT SUPPLYING POWER TO A PROCESSOR

Method and system for caching attribute data for matching attributes with physical addresses

Supporting multiple byte order formats in a computer system

System and method for identifying TLB entries associated with a physical address of a specified range

Restoring processor context in response to processor power-up

Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version

Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine

Explicit control of speculation

Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine

Method and system for caching attribute data for matching attributes with physical addresses

System and method to view crash dump information using a 2-d barcode

System and method for saving and restoring a processor state without executing any instructions from a first instruction set

Method and apparatus for improving segmented memory addressing

Architecture, system, and method for operating on encrypted and/or hidden information

System with secure cryptographic capabilities using a hardware specific digital secret

Architecture, system, and method for operating on encrypted and/or hidden information

Adaptive power control

Method and apparatus for handling nested faults

Adaptive power control

Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur

System and method for identifying TLB entries associated with a physical address of a specified range

Explicit control of speculation

Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold

Method and system for caching attribute data for matching attributes with physical addresses

System and method for identifying TLB entries associated with a physical address of a specified range

Method and apparatus for improving segmented memory addressing

Method of changing modes of code generation

Use of MTRR and page attribute table to support multiple byte order formats in a computer system

Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions

Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine

Adaptive power control

Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation

Method and system for caching attribute data for matching attributes with physical addresses

Method and system for implementing a floating point compare using recorded flags

System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored

Method of determining a mode of code generation

Method and apparatus for improving segmented memory addressing

System and method for identifying TLB entries associated with a physical address of a specified range