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Inventor profile of:

Bharat M. Pathak

City:

Folsom, California

Country:

United States

Published Applications:

7

Last publication date:

2023-08-24

Top Assignees for applications by Bharat M. Pathak

The entities that hold a legal rights for patent applications filed by inventor Pathak Bharat M.:

  • INTEL CORPORATION 3 Santa Clara, CA United States

Recent patent applications by Pathak Bharat M.

Bharat M. Pathak from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-08-24
US20230266910A1
Physics

METHOD AND APPARATUS TO SELECT A PLANE IN A NAND FLASH DIE TO STORE A READ-ONLY RESERVED BLOCK

#2 | 2020-08-06
US20200250028A1
Physics

Memory programming techniques

#3 | 2020-03-19
US20200090743A1
Physics

SYSTEM AND METHOD FOR PERFORMING A CONCURRENT MULTIPLE PAGE READ OF A MEMORY ARRAY

#4 | 2019-07-25
US20190227751A1
Physics

STORAGE SYSTEM WITH RECONFIGURABLE NUMBER OF BITS PER CELL

#5 | 2019-02-07
US20190043564A1
Physics

System and method for performing a concurrent multiple page read of a memory array

#6 | 2018-04-05
US20180095689A1
Physics

Method and apparatus for avoiding bus contention after initialization failure

#7 | 2006-12-14
US20060282643A1
Physics

Transparent low-density mode for multi-level cell flash memory devices

InventorID:

2158289 ⎘

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