Plano, Texas
United States
28
2024-04-18
The entities that hold a legal rights for patent applications filed by inventor Kraft Robert:
Robert Kraft from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:
PIEZOELECTRIC BULK LAYERS WITH TILTED C-AXIS ORIENTATION AND METHODS FOR MAKING THE SAME
#2 | 2022-10-13Piezoelectric bulk layers with tilted c-axis orientation and methods for making the same
#3 | 2022-08-25PIEZOELECTRIC BULK LAYERS WITH TILTED C-AXIS ORIENTATION AND METHODS FOR MAKING THE SAME
#4 | 2021-03-18Piezoelectric bulk layers with tilted c-axis orientation and methods for making the same
#5 | 2019-09-26Method for manufacturing piezoelectric bulk layers with tilted c-axis orientation
#6 | 2019-09-26Piezoelectric bulk layers with tilted c-axis orientation and methods for making the same
#7 | 2018-04-19Wafer-level-packaged BAW devices with surface mount connection structures
#8 | 2009-08-06Ferroelectric capacitor manufacturing process
#9 | 2009-01-15Systems and methods that selectively modify liner induced stress
#10 | 2008-11-20Formation of a silicon oxide interface layer during silicon carbide etch stop deposition to promote better dielectric stack adhesion
#11 | 2008-01-17Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability
#12 | 2007-12-27Method for cleaning post-etch noble metal residues
#13 | 2007-12-20SEMICONDUCTIVE DEVICE HAVING RESIST POISON ALUMINUM OXIDE BARRIER AND METHOD OF MANUFACTURE
#14 | 2007-05-10Method of fabricating a microelectronic device using electron beam treatment to induce stress
#15 | 2007-02-22Methods to facilitate etch uniformity and selectivity
#16 | 2007-02-08Energy beam treatment to improve packaging reliability
#17 | 2006-11-23Interconnect structure including a silicon oxycarbonitride layer
#18 | 2006-11-23Energy beam treatment to improve the hermeticity of a hermetic layer
#19 | 2006-10-10Via formation for damascene metal conductors in an integrated circuit
#20 | 2006-08-08Method of passivating and/or removing contaminants on a low-k dielectric/copper surface
#21 | 2006-08-03Systems and methods that selectively modify liner induced stress
#22 | 2006-06-08Method for reducing line edge roughness for conductive features
#23 | 2006-03-02Method for patterning sub-lithographic features in semiconductor manufacturing
#24 | 2006-01-10Dual damascene pattern liner
#25 | 2005-11-17Plasma treatment for silicon-based dielectrics
#26 | 2005-11-03In-situ etch-stop etch and ashing in association with damascene processing in forming semiconductor interconnect structures
#27 | 2005-05-31BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control
#28 | 2005-03-29Process flow for dual damescene interconnect structures
2168790 ⎘