Stephan Kronholz

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

Strain engineering in semiconductor devices by using a piezoelectric material

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer

PFET DEVICES WITH DIFFERENT STRUCTURES AND PERFORMANCE CHARACTERISTICS

Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions

Transistor with embedded Si/Ge material having reduced offset and superior uniformity

Methods of forming a layer of silicon on a layer of silicon/germanium

Superior stability of characteristics of transistors having an early formed high-K metal gate

ADJUSTING OF STRAIN CAUSED IN A TRANSISTOR CHANNEL BY SEMICONDUCTOR MATERIAL PROVIDED FOR THE THRESHOLD ADJUSTMENT

Horizontal epitaxy furnace for channel SiGe formation

TMAH RECESS FOR SILICON GERMANIUM IN POSITIVE CHANNEL REGION FOR CMOS DEVICE

Replacement gate process flow for highly scaled semiconductor devices

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY EMPLOYING A SPIN-ON GLASS MATERIAL OR A FLOWABLE OXIDE MATERIAL

METHODS OF FORMING STEPPED ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES USING A SPACER TECHNIQUE

Methods of forming isolation structures for semiconductor devices

Epitaxial channel formation methods and structures

Methods for PFET fabrication using APM solutions

Methods for pFET fabrication using APM solutions

Methods of Forming Faceted Stress-Inducing Stressors Proximate the Gate Structure of a Transistor

NFET Device with Tensile Stressed Channel Region and Methods of Forming Same

REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Semiconductor device with reduced threshold variability having a threshold adjusting semiconductor alloy in the device active region

Methods of epitaxially forming materials on transistor devices

Methods of forming PEET devices with different structures and performance characteristics

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

Method of protecting STI structures from erosion during processing operations

PMOS threshold voltage control by germanium implantation

Process flow to reduce hole defects in P-active regions and to reduce across-wafer threshold voltage scatter

Enhancing interface characteristics between a channel semiconductor alloy and a gate dielectric by an oxidation process

Reduced threshold voltage-width dependency and reduced surface topography in transistors comprising high-k metal gate electrode structures by a late carbon incorporation

Early embedded silicon germanium with insitu boron doping and oxide/nitride proximity spacer

Transistor with an embedded strain-inducing material having a gradually shaped configuration

Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas

Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material

High-K metal gate electrode structures formed by cap layer removal without sacrificial spacer

Transistor Comprising an Embedded Sigma-Shaped Semiconductor Alloy Having Superior Uniformity

Formation of a channel semiconductor alloy by a nitride hard mask layer and an oxide mask

Semiconductor devices comprising a channel semiconductor alloy formed with reduced STI topography

Embedded sigma-shaped semiconductor alloys formed in transistors by applying a uniform oxide layer prior to cavity etching

PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACKS AND AN EMBEDDED STRESSOR BY PERFORMING A SECOND EPITAXY STEP

SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME

Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devices

Transistor with Embedded Strain-Inducing Material and Dummy Gate Electrodes Positioned Adjacent to the Active Region

Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device

Semiconductor device comprising high-k metal gate electrode structures and precision eFuses formed in the active semiconductor material

Transistor with embedded Si/Ge material having reduced offset and superior uniformity

Test structure for controlling the incorporation of semiconductor alloys in transistors comprising high-k metal gate electrode structures

Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth

Reduced STI loss for superior surface planarity of embedded stressors in densely packed semiconductor devices

Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition

Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

SILICON-BASED SEMICONDUCTOR DEVICE COMPRISING eFUSES FORMED BY AN EMBEDDED SEMICONDUCTOR ALLOY

Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation

Performance enhancement in transistors comprising high-K metal gate stack by reducing a width of offset spacers

Enhancing interface characteristics between a channel semiconductor alloy and a gate dielectric by an oxidation process

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode

Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices

Formation of a channel semiconductor alloy by depositing a hard mask for the selective epitaxial growth

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

Method of manufacturing a CMOS device including molecular storage elements in a via level

Enhancing selectivity during formation of a channel semiconductor alloy by a wet oxidation process

SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU N-DOPED SEMICONDUCTOR MATERIAL

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Semiconductor element formed in a crystalline substrate material and comprising an embedded in situ doped semiconductor material

Enhancing deposition uniformity of a channel semiconductor alloy by an in situ etch process

Enhancing uniformity of a channel semiconductor alloy by forming STI structures after the growth process

Reducing silicide resistance in silicon/germanium-containing drain/source regions of transistors

Adjusting of a non-silicon fraction in a semiconductor alloy during transistor fabrication by an intermediate oxidation process

Strain engineering in semiconductor devices by using a piezoelectric material

Integration of semiconductor alloys in PMOS and NMOS transistors by using a common cavity etch process

Transistor comprising an embedded semiconductor alloy in drain and source regions extending under the gate electrode

Reduction of thickness variations of a threshold semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy

Transistor with an embedded strain-inducing material having a gradually shaped configuration

Adjusting of strain caused in a transistor channel by semiconductor material provided for threshold adjustment

Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities

Transistor device comprising an embedded semiconductor alloy having an asymmetric configuration

Transistor with embedded Si/Ge material having reduced offset to the channel region

In situ monitoring of metal contamination during microstructure processing

Method for structured application of molecules to a strip conductor and molecular memory matrix