Plano, Texas
United States
51
2026-05-28
The entities that hold a legal rights for patent applications filed by inventor Hao Pinghai:
Pinghai Hao from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SEMICONDUCTOR DEVICES WITH FIELD PLATE SPACER OVER STI
#2 | 2025-02-20GALLIUM NITRIDE TRANSISTOR WITH A DOPED REGION
#3 | 2024-10-31SEMICONDUCTOR DEVICES WITH SELECTIVELY DOPED GATE ELECTRODE STRUCTURE
#4 | 2023-11-16Gallium nitride transistor with a doped region
#5 | 2021-05-27Gallium nitride transistor with a doped region
#6 | 2020-06-11Transistor with multiple GaN-based alloy layers
#7 | 2020-05-21Gallium nitride transistor with a doped region
#8 | 2020-02-27HEMT wafer probe current collapse screening
#9 | 2019-05-23Recessed solid state apparatuses
#10 | 2018-11-20Recessed solid state apparatuses
#11 | 2017-10-19High voltage CMOS with triple gate oxide
#12 | 2016-11-03Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
#13 | 2016-07-07Single photomask high precision thin film resistor
#14 | 2015-11-12Low cost transistors
#15 | 2015-11-12High voltage CMOS with triple gate oxide
#16 | 2015-09-03Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
#17 | 2015-09-03Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
#18 | 2014-09-11Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
#19 | 2014-07-03Single photomask high precision thin film resistor
#20 | 2014-07-03Low cost transistors
#21 | 2014-07-03DEMOS formed with a through gate implant
#22 | 2014-03-06JFET having width defined by trench isolation
#23 | 2013-06-20High voltage transistor using diluted drain
#24 | 2013-05-02High voltage CMOS with triple gate oxide
#25 | 2012-03-29Quasi-vertical gated NPN-PNP ESD protection device
#26 | 2011-12-22High voltage transistor using diluted drain
#27 | 2010-10-21GATE SELF-ALIGNED LOW NOISE JFET
#28 | 2010-07-08Symmetrical bi-directional semiconductor ESD protection device
#29 | 2010-06-24Low noise JFET
#30 | 2010-02-11Implanted well breakdown in high voltage devices
#31 | 2010-02-11Reduced area single poly EEPROM
#32 | 2010-02-11Integration of high voltage JFET in linear bipolar CMOS process
#33 | 2010-02-11Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process
#34 | 2009-07-02Quasi-vertical gated NPN-PNP ESD protection device
#35 | 2008-10-16Low noise JFET
#36 | 2008-09-11Gate self aligned low noise JFET
#37 | 2007-09-20Semiconductor device incorporating fluorine into gate dielectric
#38 | 2007-07-17Fabrication of an OTP-EPROM having reduced leakage current
#39 | 2007-06-26Drain extended MOS devices with self-aligned floating region and fabrication methods therefor
#40 | 2007-04-12Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device
#41 | 2006-12-21Methods of fabricating high voltage devices
#42 | 2006-05-16Semiconductor device including a dielectric layer having a gettering material located therein and a method of manufacture therefor
#43 | 2005-09-29Reduction of channel hot carrier effects in transistor devices
#44 | 2005-09-08EEPROM with etched tunneling window
#45 | 2005-07-14JFET structure for integrated circuit and fabrication method
#46 | 2005-06-23Method for manufacturing a MOS transistor having reduced 1/f noise
#47 | 2005-04-26Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same
#48 | 2005-03-31Integrated circuit device with a vertical JFET
#49 | 2005-03-24Reduction of channel hot carrier effects in transistor devices
#50 | 2005-03-24Depletion drain-extended MOS transistors and methods for making the same
#51 | 2005-03-01JFET structure for integrated circuit and fabrication method
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