GYEONGGI-DO
South Korea
35
2025-10-23
The entities that hold a legal rights for patent applications filed by inventor PARK KI TAE:
KI TAE PARK from GYEONGGI-DO, KR has applied for patents for these inventions. The list has both pending applications and granted patents:
CONTACTLESS COUPLER, PRECAST STRUCTURE AND PRECAST STRUCTURE CONSTRUCTION METHOD USING THE SAME
#2 | 2018-05-31Heat shrinkable tube-covered rebar and method of preventing rebar from corroding using the same
#3 | 2011-09-29Method of erasing in non-volatile memory device
#4 | 2011-04-21NAND flash memory device having dummy memory cells and methods of operating same
#5 | 2010-10-28Method of erasing in non-volatile memory device
#6 | 2010-10-283-level non-volatile semiconductor memory device and method of driving the same
#7 | 2010-10-21Semiconductor memory device
#8 | 2010-05-20Multi-level non-volatile memory device, system and method with state-converted data
#9 | 2010-01-07Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same
#10 | 2009-11-26FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
#11 | 2009-08-20Methods of Restoring Data in Flash Memory Devices and Related Flash Memory Device Memory Systems
#12 | 2009-05-28NAND flash memory devices having shielding lines between wordlines and selection lines
#13 | 2009-04-16NAND flash memory device having dummy memory cells and methods of operating same
#14 | 2009-02-26Nonvolatile semiconductor memories for preventing read disturbance and reading methods thereof
#15 | 2009-01-08Non-volatile memory system including spare array and method of erasing a block in the same
#16 | 2008-12-25Semiconductor memory device
#17 | 2008-12-25Non-volatile memory device and method of operating
#18 | 2008-12-18Flash memory devices having three dimensional stack structures and methods of driving same
#19 | 2008-12-11Method of erasing in non-volatile memory device
#20 | 2008-10-30Memory array architecture for a memory device and method of operating the memory array architecture
#21 | 2008-07-103-level non-volatile semiconductor memory device and method of driving the same
#22 | 2008-05-22Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same
#23 | 2008-04-24Methods of restoring data in flash memory devices and related flash memory device memory systems
#24 | 2008-04-10Programming and reading five bits of data in two non-volatile memory cells
#25 | 2008-03-27Flash memory device and method of programming the same
#26 | 2007-09-13Memory cell array structures in NAND flash memory devices
#27 | 2007-08-23Non-volatile memory devices that utilize mirror-image programming techniques to inhibit program coupling noise and methods of programming same
#28 | 2007-02-08Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same
#29 | 2007-02-013-level non-volatile semiconductor memory device and method of driving the same
#30 | 2006-12-14NAND flash memory devices having shielding lines between wordlines and selection lines
#31 | 2006-10-26NAND flash memory device having dummy memory cells and methods of operating same
#32 | 2006-09-21Non-volatile memory device having charge trap layer and method of fabricating the same
#33 | 2006-09-07Memory array architecture for a memory device and method of operating the memory array architecture
#34 | 2006-08-17Two-bit non-volatile memory devices including independently-controllable gate electrodes and methods for fabricating the same
#35 | 2005-01-20Deck-to-girder connections for precast or prefabricated bridge decks
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