Folsom, California
United States
48
2026-02-05
The entities that hold a legal rights for patent applications filed by inventor Vemulapalli Vikranth:
Vikranth Vemulapalli from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:
GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A GRAPHICS ENVIRONMENT
#2 | 2025-07-17GRAPHICS PROCESSOR MID-THREAD PREEMPTION
#3 | 2025-07-17BINDLESS THREAD DISPATCH MID-THREAD PREEMPTION ON A GRAPHICS PROCESSOR
#4 | 2025-06-26SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
#5 | 2025-06-19MULTIPLE REGISTER ALLOCATION SIZES FOR THREADS
#6 | 2025-03-27ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
#7 | 2025-03-27SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
#8 | 2025-02-27SCALAR CORE INTEGRATION
#9 | 2025-02-20DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
#10 | 2025-02-13STACK ACCESS THROTTLING FOR SYNCHRONOUS RAY TRACING
#11 | 2024-08-01DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
#12 | 2024-05-23SUPPORTING AND LOAD BALANCING MULTIPLE DOUBLE PRECISION PIPELINES IN A GRAPHICS ENVIRONMENT
#13 | 2024-05-16INCREASING PROCESSING RESOURCES IN PROCESSING CORES OF A GRAPHICS ENVIRONMENT
#14 | 2024-02-08Scalar core integration
#15 | 2024-01-25THREAD GROUP SCHEDULING FOR GRAPHICS PROCESSING
#16 | 2024-01-11Disaggregation of system-on-chip (SOC) architecture
#17 | 2024-01-04Disaggregation of system-on-chip (SOC) architecture
#18 | 2023-11-09Stack access throttling for synchronous ray tracing
#19 | 2023-11-02Sparse optimizations for a matrix accelerator architecture
#20 | 2023-03-23GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A GRAPHICS ENVIRONMENT
#21 | 2023-02-16Data prefetching for graphics data processing
#22 | 2023-01-26Scalar core integration
#23 | 2022-12-29Multiple register allocation sizes for threads
#24 | 2022-09-29HIGH PERFORMANCE CONSTANT CACHE AND CONSTANT ACCESS MECHANISMS
#25 | 2022-08-18Systems and methods for improving cache efficiency and utilization
#26 | 2022-08-18Thread group scheduling for graphics processing
#27 | 2022-06-16Enabling product SKUs based on chiplet configurations
#28 | 2022-06-09Disaggregation of system-on-chip (SOC) architecture
#29 | 2022-06-09Systems and methods for improving cache efficiency and utilization
#30 | 2022-05-19METHOD AND APPARATUS FOR MINIMALLY INTRUSIVE INSTRUCTION POINTER-AWARE PROCESSING RESOURCE ACTIVITY PROFILING
#31 | 2022-02-03Disaggregation of system-on-chip (SOC) architecture
#32 | 2021-12-02Sparse optimizations for a matrix accelerator architecture
#33 | 2021-11-11Scalar core integration
#34 | 2021-08-19Enabling product SKUS based on chiplet configurations
#35 | 2021-08-19Data prefetching for graphics data processing
#36 | 2021-05-06Disaggregation of System-On-Chip (SOC) architecture
#37 | 2021-04-01Method and apparatus for minimally intrusive instruction pointer-aware processing resource activity profiling
#38 | 2021-02-04Sparse optimizations for a matrix accelerator architecture
#39 | 2020-09-17Disaggregation of SOC architecture
#40 | 2020-09-17Enabling product SKUs based on chiplet configurations
#41 | 2020-09-17Scalar core integration
#42 | 2020-09-17Preemptive page fault handling
#43 | 2020-09-17Data prefetching for graphics data processing
#44 | 2020-09-17Thread group scheduling for graphics processing
#45 | 2020-09-17TRANSACTIONAL PAGE FAULT HANDLING
#46 | 2020-02-06Single input multiple data processing mechanism
#47 | 2019-08-29Fusion of SIMD Processing Units
#48 | 2018-06-21Single input multiple data processing mechanism
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