Radebeul
Germany
22
2019-10-10
The entities that hold a legal rights for patent applications filed by inventor Grasshoff Gunter:
Gunter Grasshoff from Radebeul, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Semiconductor devices having silicon/germanium active regions with different germanium concentrations
#2 | 2019-10-10Semiconductor devices including Si/Ge active regions with different Ge concentrations
#3 | 2019-02-07Semiconductor devices and manufacturing techniques for reduced aspect ratio of neighboring gate electrode lines
#4 | 2018-10-16Semiconductor device comprising trench isolation
#5 | 2017-11-23HIGH-VOLTAGE TRANSISTOR DEVICE
#6 | 2016-03-03Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor
#7 | 2016-02-25Methods of forming a gate cap layer above a replacement gate structure
#8 | 2013-07-18Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer
#9 | 2013-06-20Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure
#10 | 2013-05-02Methods of forming conductive structures using a spacer erosion technique
#11 | 2012-03-13Etch methods for semiconductor device fabrication
#12 | 2011-02-03Using high-k dielectrics as highly selective etch stop materials in semiconductor devices
#13 | 2010-06-03Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure
#14 | 2010-02-04TRANSISTOR HAVING A STRAINED CHANNEL REGION CAUSED BY HYDROGEN-INDUCED LATTICE DEFORMATION
#15 | 2009-12-31CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor
#16 | 2009-03-05Method of forming CMOS device having gate insulation layers of different type and thickness
#17 | 2007-10-04Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process
#18 | 2006-02-28Signal layer for generating characteristic optical plasma emissions
#19 | 2005-11-29Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process
#20 | 2005-04-12Advanced process control for a manufacturing process of a plurality of products with minimized control degradation after re-initialization upon occurrence of reset events
#21 | 2005-04-05Methods for producing a highly doped electrode for a field effect transistor
#22 | 2005-01-04System and method for wafer-based controlled patterning of features with critical dimensions
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