Rovio
Switzerland
48
2026-05-28
The entities that hold a legal rights for patent applications filed by inventor BOESCH Thomas:
Thomas BOESCH from Rovio, CH has applied for patents for these inventions. The list has both pending applications and granted patents:
INPUT FILTERING STAGE FOR PROCESSING UNIT IN HARDWARE ACCELERATOR
#2 | 2026-03-12ADAPTIVE ARCHITECTURE FOR NEAR-MEMORY COMPUTING SHARING INACTIVE IN-MEMORY COMPUTING DEVICES
#3 | 2025-10-28Adaptive buffer sharing in multi-core reconfigurable streaming-based architectures
#4 | 2025-10-02NEURAL NETWORK HARDWARE ACCELERATOR CIRCUIT WITH REQUANTIZATION CIRCUITS
#5 | 2025-06-26STREAM-BASED MODULAR AND SCALABLE HW ACCELERATOR SUB-SYSTEM WITH DESIGN-TIME PARAMETRIC RECONFIGURABLE NPU CORES
#6 | 2025-05-22SELF-CONTAINED AND CONFIGURABLE DEBUGGING MECHANISM FOR STREAM-BASED HARDWARE ACCELERATORS
#7 | 2024-10-24CONFIGURABLE STREAM SWITCH WITH VIRTUAL CHANNELS FOR THE SHARING OF I/O PORTS IN STREAM-BASED ARCHITECTURES
#8 | 2024-10-03DEVICE AND METHOD FOR ON-THE-FLY PROCESSING CHAIN RECONFIGURATION IN A STREAMING BASED NEURAL PROCESSING UNIT
#9 | 2024-10-03NEURAL NETWORK INCLUDING LOCAL STORAGE UNIT
#10 | 2024-10-03NEURAL NETWORK INCLUDING LOCAL STORAGE UNIT
#11 | 2024-08-22RECONFIGURABLE, STREAMING-BASED CLUSTERS OF PROCESSING ELEMENTS, AND MULTI-MODAL USE THEREOF
#12 | 2024-08-22RECONFIGURABLE, STREAMING-BASED CLUSTERS OF PROCESSING ELEMENTS, AND MULTI-MODAL USE THEREOF
#13 | 2024-07-04FLEXIBLE DATA STREAM ENCRYPTION/DECRYPTION ENGINE FOR STREAM-ORIENTED NEURAL NETWORK ACCELERATORS
#14 | 2024-07-04PROGRAMMABLE HARDWARE ACCELERATOR CONTROLLER
#15 | 2024-02-08TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM
#16 | 2024-01-11ITERATION ENGINE FOR THE COMPUTATION OF LARGE KERNELS IN CONVOLUTIONAL ACCELERATORS
#17 | 2023-12-28ACCELERATION OF 1X1 CONVOLUTIONS IN CONVOLUTIONAL NEURAL NETWORKS
#18 | 2023-11-02Computing system power management device, system and method
#19 | 2023-06-29Vector quantization decoding hardware unit for real-time dynamic decompression for parameters of neural networks
#20 | 2023-06-15Data volume sculptor for deep learning acceleration
#21 | 2023-05-18Arithmetic unit for deep learning acceleration
#22 | 2023-05-04Pooling unit for deep learning acceleration
#23 | 2023-03-16Convolution acceleration with embedded vector decompression
#24 | 2023-03-02NEURAL NETWORK HARDWARE ACCELERATOR CIRCUIT WITH REQUANTIZATION CIRCUITS
#25 | 2022-08-25Tagged memory operated at lower vmin in error tolerant system
#26 | 2022-03-31Reconfigurable hardware buffer in a neural networks accelerator framework
#27 | 2021-12-23Convolution acceleration with embedded vector decompression
#28 | 2021-08-26Pooling unit for deep learning acceleration
#29 | 2021-08-19Vector quantization decoding hardware unit for real-time dynamic decompression for parameters of neural networks
#30 | 2021-08-05Streaming access memory device, system and method
#31 | 2021-06-24Data volume sculptor for deep learning acceleration
#32 | 2021-06-17Computing system power management device, system and method
#33 | 2021-03-18Variable clock adaptation in neural network processors
#34 | 2021-03-11Tool to create a reconfigurable interconnect framework
#35 | 2021-03-11Tagged memory operated at lower vmin in error tolerant system
#36 | 2020-10-01Hardware accelerator method, system and device
#37 | 2020-10-01Convolutional network hardware accelerator device, system and method
#38 | 2020-08-27Reconfigurable interconnect
#39 | 2019-12-12Tool to create a reconfigurable interconnect framework
#40 | 2019-11-07Reconfigurable interconnect
#41 | 2019-08-29Data volume sculptor for deep learning acceleration
#42 | 2019-08-29Arithmetic unit for deep learning acceleration
#43 | 2019-08-29Acceleration unit for a deep learning engine
#44 | 2018-07-05Configurable accelerator framework including a stream switch having a plurality of unidirectional stream links
#45 | 2018-07-05Hardware accelerator engine
#46 | 2018-07-05Tool to create a reconfigurable interconnect framework
#47 | 2018-07-05Deep convolutional network heterogeneous architecture
#48 | 2018-07-05Reconfigurable interconnect
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