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Inventor profile of:

Jayesh Gaur

City:

Bengaluru

Country:

India

Published Applications:

8

Last publication date:

2026-04-09

Top Assignees for applications by Jayesh Gaur

The entities that hold a legal rights for patent applications filed by inventor Gaur Jayesh:

INTEL CORPORATION 5 Santa Clara, CA United States

Recent patent applications by Gaur Jayesh

Jayesh Gaur from Bengaluru, IN has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-09

US20260099330A1

Apparatus and Method for Elimination of Load Execution by Combining Loads Directed to the Same Cache Line

#2 | 2026-01-01

US20260003626A1

Methods and Apparatus for Efficiently Processing Load Instruction Sequences

#3 | 2025-09-25

US20250298623A1

BANDWIDTH AWARE SIMULTANEOUS MULTI-THREADING

#4 | 2025-06-19

US20250199813A1

APPARATUS AND METHOD FOR PROFILE-OPTIMIZED LOOPS

#5 | 2019-08-08

US20190243760A1

Memory-efficient last level cache architecture

#6 | 2018-08-16

US20180232311A1

Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time

#7 | 2018-08-16

US20180232235A1

Efficient hardware-based extraction of program instructions for critical paths

#8 | 2018-07-19

US20180203799A1

Memory-efficient last level cache architecture

InventorID:

2247501 ⎘