Barsinghausen
Germany
22
2020-09-10
The entities that hold a legal rights for patent applications filed by inventor Hecht Volker:
Volker Hecht from Barsinghausen, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
SEU stabilized memory cells
#2 | 2019-07-25VERTICAL RESISTOR BUFFERED MULTIPLEXER BUSKEEPER
#3 | 2019-07-25VERTICAL RESISTOR BASED SRAM CELLS
#4 | 2019-05-30Efficient lookup table modules for user-programmable integrated circuits
#5 | 2018-04-19Circuits and methods for preventing over-programming of ReRAM-based memory cells
#6 | 2018-03-29Three-transistor resistive random access memory cells
#7 | 2017-07-11Three-transistor resistive random access memory cells
#8 | 2013-05-02RAM block designed for efficient ganging
#9 | 2010-12-30Inverting flip-flop for use in field programmable gate arrays
#10 | 2010-12-16Circuits and methods for testing FPGA routing switches
#11 | 2010-10-19Inverting flip-flop for use in field programmable gate arrays
#12 | 2010-07-29Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit
#13 | 2010-06-24PLD providing soft wakeup logic
#14 | 2010-03-11Circuits and methods for testing FPGA routing switches
#15 | 2008-09-11FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK
#16 | 2008-06-26Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
#17 | 2007-07-19Field programmable gate array long line routing network
#18 | 2007-05-01Field programmable gate array long line routing network
#19 | 2007-04-26Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage
#20 | 2007-01-09Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage
#21 | 2006-11-02Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
#22 | 2006-09-12Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
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