ACTEL CORPORATION

Fast carry lookahead circuits

Enhanced field programmable gate array

Non-volatile two-transistor programmable logic cell and array layout

Staggered I/O groups for integrated circuits

Clustered field programmable gate array architecture

Field programmable gate array architecture having Clos network-based input interconnect

Field programmable gate array including a non-volatile user memory and method for programming

Architecture and interconnect scheme for programmable logic circuits

Method and apparatus for universal program controlled bus architecture

Programmable logic device adapted to enter a low-power mode

Push-pull programmable logic device cell

Back to back resistive random access memory cells

Resistive RAM devices for programmable logic devices

Inverting flip-flop for use in field programmable gate arrays

Single event transient mitigation and measurement in integrated circuits

Circuits and methods for testing FPGA routing switches

Logic module including versatile adder for FPGA

Inverting flip-flop for use in field programmable gate arrays

Isolated-nitride-region non-volatile memory cell and fabrication method

Enhanced field programmable gate array

Array and control method for flash based FPGA cell

Logic module including versatile adder for FPGA

Radiation-tolerant flash-based FPGA memory cells

Isolated-nitride-region non-volatile memory cell and fabrication method

Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit

Push-pull memory cell configured for simultaneous programming of n-channel and p-channel non-volatile transistors

(N+1) input flip-flop packing with logic in FPGA architectures

Programmable delay line compensated for process, voltage, and temperature

Programmable logic device with programmable wakeup pins

PLD providing soft wakeup logic

Push-pull FPGA cell

Programmable logic device with a microcontroller-based control system

Flexible carry scheme for field programmable gate arrays

(N+1) input flip-flop packing with logic in FPGA architectures

Programmable delay line compensated for process, voltage, and temperature

Non-volatile memory array having drain-side segmentation for an FPGA device

Split gate memory cell for programmable circuit device

Programmable logic device with a microcontroller-based control system

Circuits and methods for testing FPGA routing switches

Apparatus and method for initializing an integrated circuit device and activating a function of the device once an input power supply has reached a threshold voltage

Reduced-edge radiation-tolerant non-volatile transistor memory cells

Mixed signal system-on-a-chip integrated simultaneous multiple sample/hold circuits and embedded analog comparators

Non-volatile two-transistor programmable logic cell and array layout

Flexible carry scheme for field programmable gate arrays

Quadratic and cubic compensation of sigma-delta D/A and A/D converters

Flash-based FPGA with secure reprogramming

Programmable system on a chip for power-supply voltage and current monitoring and control

High-voltage dual-polarity I/O p-well pump ESD protection circuit

Programmable system on a chip

Reconfigurable delta sigma analog-to-digital converter and customized digital filters with embedded flash FPGA and flash memory

Programmable logic device adapted to enter a low-power mode

Flash-based FPGA with secure reprogramming

Non-volatile two-transistor programmable logic cell and array layout

Method for secure delivery of configuration data for a programmable logic device

Single event transient mitigation and measurement in integrated circuits

Non-volatile two-transistor programmable logic cell and array layout

Volatile data storage in a non-volatile memory cell array

Single event transient mitigation and measurement in integrated circuits

Method and apparatus for universal program controlled bus architecture

Encryption for a stream file in an FPGA integrated circuit

Nonvolatile memory integrated circuit having assembly buffer and bit-line driver, and method of operation thereof

Non-volatile two-transistor programmable logic cell and array layout

Isolation scheme for static and dynamic FPGA partial programming

FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation

Radiation tolerant SRAM bit

Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture

Circuit and method for supplying programming potential at voltages larger than BVDss of programming transistors

Non-volatile two-transistor programmable logic cell and array layout

Non-volatile two-transistor programmable logic cell and array layout

Programmable system on a chip for power-supply voltage and current monitoring and control

Field programmable gate array and microcontroller system-on-a-chip

Non-volatile memory with source-side column select

Delay locked loop for an FPGA architecture

Apparatus for testing a phrase-locked loop in a boundary scan enabled device

Error-detecting and correcting FPGA architecture

Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge

Delay locked loop for an FPGA architecture

Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array

Non-volatile two-transistor programmable logic cell and array layout

Clock-generator architecture for a programmable-logic-based system on a chip

Programmable system on a chip for temperature monitoring and control

Apparatus and method for reducing leakage of unused buffers in an integrated circuit

Deglitching circuits for a radiation-hardened static random access memory based programmable architecture

ESD protection structure for I/O pad subject to both positive and negative voltages

Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material

System-on-a-chip integrated circuit including dual-function analog and digital inputs

SRAM cell controlled by flash memory cell

Architecture and interconnect scheme for programmable logic circuits

Block symmetrization in a field programmable gate array

Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks

Multi-level routing architecture in a field programmable gate array having transmitters and receivers

Apparatus for interfacing and testing a phase locked loop in a field programmable gate array