Toronto
Canada
162
2025-12-04
The entities that hold a legal rights for patent applications filed by inventor Lewis David:
David Lewis from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
MULTIPLYING ACCUMULATION WITH SHIFTING BASED ON MAXIMUM MANTISSA PRODUCT BITLENGTH
#2 | 2019-10-22Configuring programmable integrated circuit device resources as processors
#3 | 2019-06-04Method and apparatus for performing symbolic timing analysis with spatial variation
#4 | 2019-01-08Omnibus logic element
#5 | 2018-04-10Tristate multiplexers with immunity to aging effects
#6 | 2018-02-13Techniques for bypassing defects in rows of circuits
#7 | 2017-11-21Configurable storage blocks with embedded first-in first-out and delay line circuitry
#8 | 2017-11-09STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS
#9 | 2017-11-07Circuitry for implementing multi-mode redundancy and arithmetic functions
#10 | 2017-10-05Pipelined interconnect circuitry with double data rate interconnections
#11 | 2017-07-04Metastability-hardened synchronization circuit
#12 | 2017-06-27Pipelined interconnect circuitry with double data rate interconnections
#13 | 2017-05-23Structures for LUT-based arithmetic in PLDs
#14 | 2017-05-23Integrated circuits with improved register circuitry
#15 | 2017-03-21Error detection and correction circuitry
#16 | 2017-02-28Methods and apparatus for detecting memory bit corruption on an integrated circuit
#17 | 2017-01-24Configuring programmable integrated circuit device resources as processing elements
#18 | 2016-11-24Routing and programming for resistive switch arrays
#19 | 2016-11-22First-in-first-out memory with dual memory banks
#20 | 2016-11-15Omnibus logic element
#21 | 2016-10-25Transition accelerator circuitry
#22 | 2016-08-18CLOCKING FOR PIPELINED ROUTING
#23 | 2016-07-26Heterogeneous programmable device and configuration software adapted therefor
#24 | 2016-06-14Multichip module with reroutable inter-die communication
#25 | 2016-06-07Circuitry for implementing multi-mode redundancy and arithmetic functions
#26 | 2016-05-10Memory error detection circuitry
#27 | 2016-04-07Integrated circuit device configuration methods adapted to account for retiming
#28 | 2016-02-11Routing and programming for resistive switch arrays
#29 | 2015-11-10Automatic asynchronous signal pipelining
#30 | 2015-11-03Memory blocks with shared address bus circuitry
#31 | 2015-10-20Apparatus for field-programmable gate array with configurable architecture and associated methods
#32 | 2015-10-20Routing and programming for resistive switch arrays
#33 | 2015-08-04Pipelined direct drive routing fabric
#34 | 2015-05-14Clocking for pipelined routing
#35 | 2015-05-12Heterogeneous programmable device and configuration software adapted therefor
#36 | 2015-05-05Method and apparatus for reducing power spikes caused by clock networks
#37 | 2015-03-31Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew
#38 | 2015-02-19Metastability prediction and avoidance in memory arbitration circuitry
#39 | 2015-01-29Integrated circuit device configuration methods adapted to account for retiming
#40 | 2014-12-23Methods and circuitry for performing parallel error checking
#41 | 2014-11-25Heterogeneous programmable device and configuration software adapted therefor
#42 | 2014-11-18High speed testing of integrated circuits including resistive elements
#43 | 2014-11-06Time division multiplexed multiport memory implemented using single-port memory elements
#44 | 2014-11-04Omnibus logic element
#45 | 2014-10-30CONFIGURABLE MULTI-GATE SWITCH CIRCUITRY
#46 | 2014-10-21Integrated circuits with hold time avoidance circuitry
#47 | 2014-10-14Integrated circuit device configuration methods adapted to account for retiming
#48 | 2014-09-16Specification of latency in programmable device configuration
#49 | 2014-09-11APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS
#50 | 2014-09-09Automatic asynchronous signal pipelining
#51 | 2014-07-31PLD architecture for flexible placement of IP function blocks
#52 | 2014-07-22Structures for LUT-based arithmetic in PLDs
#53 | 2014-04-29Specification of latency in programmable device configuration
#54 | 2014-03-20Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
#55 | 2014-03-18Programmable device configuration methods adapted to account for retiming
#56 | 2014-02-04Specification of multithreading in programmable device configuration
#57 | 2013-12-12Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
#58 | 2013-12-12Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
#59 | 2013-12-12Integrated circuits with dual-edge clocking
#60 | 2013-11-26Omnibus logic element for packing or fracturing
#61 | 2013-10-15Memory error detection circuitry
#62 | 2013-10-15Method and apparatus for reducing power spikes caused by clock networks
#63 | 2013-10-03Integrated circuits with multi-stage logic regions
#64 | 2013-09-17Automatic asynchronous signal pipelining
#65 | 2013-09-03Merged tristate multiplexer
#66 | 2013-08-22PLD architecture for flexible placement of IP function blocks
#67 | 2013-08-20Memory elements with a configurable number of ports
#68 | 2013-07-11Integrated circuits with shared interconnect buses
#69 | 2013-07-04Multichip module with reroutable inter-die communication
#70 | 2013-05-02Time division multiplexed multiport memory implemented using single-port memory elements
#71 | 2012-09-06Delay circuitry
#72 | 2012-08-30Error detection and correction circuitry
#73 | 2012-08-30PLD architecture for flexible placement of IP function blocks
#74 | 2012-08-28Pulse width control circuitry
#75 | 2012-08-14Methods and systems for managing a write operation
#76 | 2012-08-07Omnibus logic element for packing or fracturing
#77 | 2012-07-10Fracturable lookup table and logic element
#78 | 2012-05-29Redundancy structures and methods in a programmable logic device
#79 | 2012-05-10Robust time borrowing pulse latches
#80 | 2012-05-08Repairable IO in an integrated circuit
#81 | 2012-04-12Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices
#82 | 2012-02-07Error correction for programmable logic integrated circuits
#83 | 2011-12-15Integrated circuits with dual-edge clocking
#84 | 2011-11-03Low-power routing multiplexers
#85 | 2011-09-22Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
#86 | 2011-08-25Apparatus and methods for adjusting performance of programmable logic devices
#87 | 2011-07-12Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
#88 | 2011-05-05Variable sized soft memory macros in structured cell arrays, and related methods
#89 | 2011-05-05Configurable time borrowing flip-flops
#90 | 2011-04-21Robust time borrowing pulse latches
#91 | 2011-04-21Configurable multi-gate switch circuitry
#92 | 2011-03-22Omnibus logic element for packing or fracturing
#93 | 2011-03-08Repairable IO in an integrated circuit
#94 | 2010-10-19Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew
#95 | 2010-10-12Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device
#96 | 2010-09-30Variable sized soft memory macros in structured cell arrays, and related methods
#97 | 2010-09-21Fracturable lookup table and logic element
#98 | 2010-09-14Memory circuits having programmable non-volatile resistors
#99 | 2010-09-09Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
#100 | 2010-05-11Programmable logic device architectures and methods for implementing logic in those architectures
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