Sreejit Chakravarty

METHOD AND SYSTEM FOR REDUCING MEMORY TEST TIME UTILIZING A BUILT-IN SELF-TEST ARCHITECTURE

Data transformations to improve ROM yield and programming time

Stored-pattern logic self-testing with serial communication

Victim port-based design for test area overhead reduction in multiport latch-based memories

Electronic design automation tool and method for employing unsensitized critical path information to reduce leakage power in an integrated circuit

SCAN TEST CIRCUITRY COMPRISING SCAN CELLS WITH FUNCTIONAL OUTPUT MULTIPLEXING

Timing error sampling generator and a method of timing testing

Logic BIST for system testing using stored patterns

Scan cell designs with serial and parallel loading of test data

SCAN CELL DESIGNS WITH SERIAL AND PARALLEL LOADING OF TEST DATA

Low cost comparator design for memory BIST

Low-cost design for register file testability

System and method for testing memory power management modes in an integrated circuit

System and method for reducing the generation of inconsequential violations resulting from timing analyses

Enhanced logic built-in self-test module and method of online system testing employing the same

Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit

Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testing

Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit

Critical path monitor for an integrated circuit and method of operation thereof