LSI CORPORATION

Host based enumeration and configuration for computer expansion bus controllers

Flash memory read retry using histograms

Arbitration suspension in a SAS domain

Multi-protocol storage controller

Interface for heterogeneous PCI-e storage devices

Address decoding circuits for reducing address and memory enable setup time

Sharing of bypassed I/O transaction information

Moisture barrier for a wire bond

Data recovery in a raid controller by offloading contents of DRAM to a flash module on an SAS switch

Smart discovery model in a serial attached small computer system topology

Programmable clock spreading

Intelligent data buffering between interfaces

Analog tunneling current sensors for use with disk drive storage devices

Pattern-based loss of signal detector

Modify priority of dataset based on number of times the data set is processed by both a data detector circuit and a data decoder circuit

Systems and methods for distributed low density parity check decoding

At-speed scan testing of interface functional logic of an embedded memory or other circuit core

Methods and structure for single root input/output virtualization enhancement in peripheral component interconnect express systems

Systems and methods for shared layer data decoding

Integration of shallow trench isolation and through-substrate vias into integrated circuit designs

Extraction tool and method for determining maximum and minimum stage delays associated with integrated circuit interconnects

Receiver having limiter-enhanced data eye openings

At-speed scan testing of clock divider logic in a clock module of an integrated circuit

Storage device out-of-space handling

Margin free PVT tolerant fast self-timed sense amplifier reset circuit

Memory having sense amplifier for output tracking by controlled feedback latch

Capacitive coupled sense amplifier biased at maximum gain point

Method and system to maintain maximum performance levels in all disk groups by using controller VDs for background tasks

Receiver with dual clock recovery circuits

System and method for providing fast and efficient flushing of a forwarding database in a network processor

Non-volatile memory program failure recovery via redundant arrays

SerDes data sampling gear shifter

Pre-charge tracking of global read lines in high speed SRAM

Sync mark detection using branch metrics from data detector

Fly height control for hard disk drives

Hybrid digital/analog power amplifier

Majority-tabular post processing of quasi-cyclic low-density parity-check codes

Management of non-valid decision patterns of a soft read retry operation

Signal processing circuitry with frontend and backend circuitry controlled by separate clocks

Single-port read multiple-port write storage device using single-port memory cells

Equalization combining outputs of multiple component filters

Systems and methods for managed operational marginalization

Over-sampled signal equalizer

Multiple step non-deterministic finite automaton matching

Cache prefetch for deterministic finite automaton instructions

Expander for loop architectures

Method and system for detecting multiple expanders in an SAS topology having the same address

Method and apparatus to share a single storage drive across a large number of unique systems when data is highly redundant

Performance control in video encoding

Adaptive cancellation of voltage offset in a communication system

Receiver with distortion compensation circuit

Link rate availability based arbitration

Systems and methods for adaptive threshold pattern detection

Tag multiplication via a preamplifier interface

Low density parity check decoder with miscorrection handling

Methods and structure for using region locks to divert I/O requests in a storage controller having multiple processing stacks

Structure for non-blocking serial attached SCSI infrastructure utilizing virtual pathways

Non-deterministic finite automaton (NFA) overflow recovery that ejects an end of scan set of active states into a buffer

Multi-layer approach for frame-missing concealment in a video decoder

Systems and methods for X-sample based data processor marginalization

Switching power amplifier system for multi-path signal interleaving

Systems and methods for selective retry data retention processing

Dynamic slice resizing while encoding video

Packet data processor in a communications processor architecture

Read assist scheme for reducing read access time in a memory

Systems and methods for old data inter-track interference compensation

Concurrent true and complement signal generation

External component-less PVT compensation scheme for IO buffers

Reduction of metal fill insertion time in integrated circuit design process

Systems and methods for controlled data processor operational marginalization

System and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life

SATA data appliance for providing SATA hosts with access to a configurable number of SATA drives residing in a SAS topology

DFA-NFA hybrid

Receiver with parallel decision feedback equalizers

Overshoot suppression for input/output buffers

Scan circuitry for testing input and output functional paths of an integrated circuit

Self-sizing dynamic cache for virtualized environments

Complex NFA state matching method that matches input symbols against character classes (CCLs), and compares sequence CCLs in parallel

Harmonic ratio based defect classifier

Read channel error correction using multiple calibrators