Dublin, California
United States
31
2026-06-25
The entities that hold a legal rights for patent applications filed by inventor Lanka Narasimha:
Narasimha Lanka from Dublin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
#2 | 2026-06-25RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT
#3 | 2026-02-12PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT
#4 | 2026-02-05DIE-TO-DIE INTERCONNECT
#5 | 2025-01-09LINK LAYER-PHY INTERFACE ADAPTER
#6 | 2024-09-19ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIE) PHY
#7 | 2023-08-17TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING
#8 | 2023-07-20MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDUCTOR PACKAGE INCLUDING SAME
#9 | 2022-10-27DIE-TO-DIE ADAPTER
#10 | 2022-10-27DIE-TO-DIE INTERCONNECT
#11 | 2022-10-20PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT
#12 | 2022-10-20RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT
#13 | 2022-10-13LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) INTERCONNECTS
#14 | 2022-10-13DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
#15 | 2022-10-13STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
#16 | 2022-10-06COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT
#17 | 2022-08-25CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT
#18 | 2022-08-18CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS
#19 | 2022-08-18VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS
#20 | 2022-07-28LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT
#21 | 2022-07-14Sideband interface for die-to-die interconnects
#22 | 2022-01-13Control Apparatus, Device, Method and Computer Program for Determining a Device-Specific Supply Voltage for a Semiconductor Device
#23 | 2021-11-04PHY-based retry techniques for die-to-die interfaces
#24 | 2021-07-22LOGIC DIE IN A MULTI-CHIP PACKAGE HAVING A CONFIGURABLE PHYSICAL INTERFACE TO ON-PACKAGE MEMORY
#25 | 2021-07-22Reduction of latency impact of on-die error checking and correction (ECC)
#26 | 2021-01-07Approximate data bus inversion technique for latency sensitive applications
#27 | 2020-12-17High performance interconnect
#28 | 2020-12-17Link layer-PHY interface adapter
#29 | 2020-12-17Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output links
#30 | 2020-08-06STACKED MEMORY DEVICE WITH END TO END DATA BUS INVERSION
#31 | 2018-09-06High performance interconnect
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