Santa Clara, California
United States
45
2025-10-02
The entities that hold a legal rights for patent applications filed by inventor Tsien Benjamin:
Benjamin Tsien from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:
INTERRUPT COALESCING DURING PROCESSOR IDLE
#2 | 2025-07-17ON-DEMAND IP INITIALIZATION WITHIN POWER STATES
#3 | 2025-07-03SEGMENT CLOCK GATING
#4 | 2025-06-19REDUCED MESH LANE ROUTING
#5 | 2025-04-03ARBITRATED INTERRUPT STEERING IN HETEROGENEOUS PROCESSORS
#6 | 2025-01-30MEMORY SELF-REFRESH POWER GATING
#7 | 2025-01-02LOW POWER MEMORY STATE DURING NON-IDLE PROCESSOR STATE
#8 | 2025-01-02HETEROGENEOUS CHIPLET POWER MANAGEMENT
#9 | 2024-12-26ALLOCATION CONTROL FOR CACHE
#10 | 2024-07-04CHIPLET INTERCONNECT POWER STATE MANAGEMENT
#11 | 2024-04-04On-Demand Regulation of Memory Bandwidth Utilization to Service Requirements of Display
#12 | 2024-03-28Memory Power Performance State Optimization During Image Display
#13 | 2024-01-04Droop mitigation for an inter-chiplet interface
#14 | 2024-01-04SCHEDULING TRAINING OF AN INTER-CHIPLET INTERFACE
#15 | 2024-01-04INPUT/OUTPUT STUTTER WAKE ALIGNMENT
#16 | 2023-12-28Allocation control for cache
#17 | 2023-12-28Technique to enable simultaneous use of on-die SRAM as cache and memory
#18 | 2023-11-02Device and method for efficient transitioning to and from reduced power state
#19 | 2023-10-26Dynamic cache bypass for power savings
#20 | 2023-10-05Cross-chiplet performance data streaming
#21 | 2023-10-05Using a hardware-based controller for power state management
#22 | 2023-09-07Technique for extended idle duration for display to improve power consumption
#23 | 2023-06-29Method and apparatus for managing power states
#24 | 2023-06-15METHOD OF TASK TRANSITION BETWEEN HETEROGENOUS PROCESSORS
#25 | 2023-03-30Device and method for efficient transitioning to and from reduced power state
#26 | 2023-03-30Method and apparatus for managing a controller in a power down state
#27 | 2023-03-30METHOD AND APPARATUS FOR ISOLATING AND LATCHING GPIO OUTPUT PADS
#28 | 2023-03-23Device and method for two-stage transitioning between reduced power states
#29 | 2023-03-23Device and method for reducing save-restore latency using address linearization
#30 | 2023-02-02Technique for extended idle duration for display to improve power consumption
#31 | 2023-02-02On-demand IP initialization within power states
#32 | 2023-02-02REDUCED POWER CLOCK GENERATOR FOR LOW POWER DEVICES
#33 | 2023-02-02Hierarchical state save and restore for device with varying power states
#34 | 2022-04-28Refreshing displays using on-die cache
#35 | 2022-03-31Shared data fabric processing client reset system and method
#36 | 2022-03-24MECHANISM FOR PERFORMING DISTRIBUTED POWER MANAGEMENT OF A MULTI-GPU SYSTEM
#37 | 2021-12-30Direct mapping mode for associative cache
#38 | 2021-10-28SYSTEM-WIDE LOW POWER MANAGEMENT
#39 | 2021-07-01LONG-IDLE STATE SYSTEM AND METHOD
#40 | 2021-06-24Arbitration scheme for coherent and non-coherent memory requests
#41 | 2021-06-10Method of task transition between heterogenous processors
#42 | 2021-03-25Dynamic control of multi-region fabric
#43 | 2020-12-31METHOD AND APPARATUS FOR SERVICING AN INTERRUPT
#44 | 2020-12-10Reducing chiplet wakeup latency
#45 | 2018-10-25Input/output memory map unit and northbridge
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