Meridian, Idaho
United States
28
2026-05-28
The entities that hold a legal rights for patent applications filed by inventor Davis James E.:
James E. Davis from Meridian, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MICROELECTRONIC DEVICES AND RELATED METHODS
#2 | 2026-05-21MICROELECTRONIC DEVICE FOR DETECTING ELECTROSTATIC DISCHARGE EVENTS, AND ASSOCIATED COMPONENTS, STRUCTURES, AND METHODS
#3 | 2026-04-23BIDIRECTIONAL ELECTROSTATIC DISCHARGE DETECTOR
#4 | 2026-01-15MICROELECTRONIC DEVICES INCLUDING HEAT SINKS, AND ASSOCIATED DEVICES AND METHODS
#5 | 2025-10-02DISCHARGE CIRCUITS
#6 | 2025-06-05PLASMA INDUCED DAMAGE DETECTION OF A MEMORY DIE
#7 | 2024-11-28METHOD AND APPARATUS OF MEMORY ARRAY DEVICE WITH LOW ARCING RISK
#8 | 2024-08-29MICROELECTRONIC DEVICES INCLUDING THROUGH-SILICON VIAS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
#9 | 2024-02-29DISCHARGE CIRCUITS
#10 | 2024-02-01APPARATUS WITH VOLTAGE PROTECTION MECHANISM
#11 | 2022-11-10Apparatus with voltage protection mechanism
#12 | 2022-06-23Multi-die memory device with peak current reduction
#13 | 2021-06-17Apparatus with voltage protection mechanism
#14 | 2021-06-10Semiconductor devices with package-level configurability
#15 | 2021-02-11Memory device including circuitry under bond pads
#16 | 2020-11-26Semiconductor devices having 3-dimensional inductive structures
#17 | 2020-07-02Semiconductor devices with package-level configurability
#18 | 2020-05-14Semiconductor devices with package-level configurability
#19 | 2020-05-07Semiconductor devices having 3-dimensional inductive structures
#20 | 2020-01-30Semiconductor devices with through silicon vias and package-level configurability
#21 | 2019-11-19Semiconductor devices with through silicon vias and package-level configurability
#22 | 2019-09-05Semiconductor devices with post-probe configurability
#23 | 2019-05-16Semiconductor devices with package-level configurability
#24 | 2019-05-16Semiconductor devices with package-level configurability
#25 | 2019-05-16Semiconductor devices with post-probe configurability
#26 | 2019-05-07Semiconductor devices with post-probe configurability
#27 | 2018-12-20Method and apparatus for reducing capacitance of input/output pins of memory device
#28 | 2018-11-13Semiconductor devices with package-level configurability
2380525 ⎘