Thomas A. Piazza

Scatter/gather capable system coherent cache

Hardware based free lists for multi-rate shader

Dynamically managing memory footprint for tile based rendering

Reduced power implementation of computer instructions

Method and apparatus for SIMD structured branching

Position-only shading pipeline

Techniques for efficient GPU triangle list adjacency detection and handling

Scatter/gather capable system coherent cache

Lossy color merge for multi-sampling anti-aliasing compression

Ordering threads as groups in a multi-threaded, multi-core graphics compute system

TECHNIQUES FOR LOW ENERGY COMPUTATION IN GRAPHICS PROCESSING

Techniques for improving MSAA rendering efficiency

Recording the results of visibility tests at the input geometry object granularity

Technique to share information among different cache coherency domains

Techniques for efficient GPU triangle list adjacency detection and handling

Technique to share information among different cache coherency domains

Technique to share information among different cache coherency domains

Dynamic allocation of a buffer across multiple clients in a threaded processor

Technique to share information among different cache coherency domains

Thread queueing method and apparatus

Processing architecture having passive threads and active semaphores

Behavioral model based multi-threaded architecture

Thread ordering techniques

Dynamic allocation of a buffer across multiple clients in a threaded processor

Technique to share information among different cache coherency domains

Run length encoded digital image

Cache for a multi thread and multi core system and methods thereof

Thread queuing method and apparatus

Methods and apparatuses for compaction and/or decompaction

Z-buffering techniques for graphics rendering

Match MSB digital image compression

Pixel filtering using shared filter resource between overlay and texture mapping engines

Match MSB digital image compression

Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines

Methods and arrangements to interface memory

3-D rendering texture caching scheme

Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation

Hardware stack having entries with a data portion and associated counter

Determining a register file region based at least in part on a value in an index register

3-D rendering texture caching scheme

Memory arbiter with grace and ceiling periods and intelligent page gathering logic

Conditional instruction for a single instruction, multiple data execution engine

Render-cache controller for multithreading, multi-core graphics processor

Bandwidth reduction for rendering using vertex data

Visual and graphical data processing using a multi-threaded architecture

Processing architecture having passive threads and active semaphores

Behavioral model based multi-threaded architecture

Memory arbiter with intelligent page gathering logic