Brian D. Emberling

Method and system for thread monitoring

Method and system for workitem synchronization

Executing first instructions for smaller set of SIMD threads diverging upon conditional branch instruction

Large-kernel convolution using multiple industry-standard graphics accelerators

Handling of extra contexts for shader constants

Method for improving cache-miss performance

Capturing data and crossing clock domains in the absence of a free-running source clock

Method for improving texture cache access by removing redundant requests

Magnified texture-mapped pixel performance in a single-pixel pipeline

Method for optimizing utilization of a double-data-rate-SDRAM memory system

Controlling the propagation of a control signal by means of variable I/O delay compensation using a programmable delay circuit and detection sequence

Optimized cache structure for multi-texturing

Multi-texturing by walking an appropriately-sized supertile over a primitive

Controlling the propagation of a digital signal by means of variable I/O delay compensation using delay-tracking

Early primitive assembly and screen-space culling for multiple chip graphics system

Graphics primitive size estimation and subdivision for use with a texture accumulation buffer

Multipurpose memory system for use in a graphics system

Stalling pipelines in large designs

Design for a non-blocking cache for texture mapping

Graphics data synchronization with multiple data paths in a graphics accelerator

Graphics data accumulation for improved multi-layer texture performance

Magnified texture-mapped pixel performance in a single-pixel pipeline

Reading a selected register in a series of computational units forming a processing pipeline upon expiration of a time delay