Inventor profile of:

Devendra Natekar

City:

Chandler, Arizona

Country:

United States

Published Applications:

19

Last publication date:

2013-05-16

Top Assignees for applications by Devendra Natekar

The entities that hold a legal rights for patent applications filed by inventor Natekar Devendra:

Recent patent applications by Natekar Devendra

Devendra Natekar from Chandler, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-05-16
US20130122656A1
Electricity

Flexible interconnect pattern on semiconductor package

#2 | 2012-11-15
US20120289002A1
Electricity

Flexible interconnect pattern on semiconductor package

#3 | 2011-05-05
US20110103438A1
Electricity

Flexible interconnect pattern on semiconductor package

#4 | 2010-08-05
US20100193952A1
Electricity

Integrated circuit die containing particale-filled through-silicon metal vias with reduced thermal expansion

#5 | 2009-03-19
US20090072013A1
Electricity

NANO-SCALE PARTICLE PASTE FOR WIRING MICROELECTRONIC DEVICES USING INK-JET PRINTING

#6 | 2008-12-11
US20080303159A1
Electricity

Thin silicon based substrate

#7 | 2008-10-30
US20080265391A1
Electricity

Etched interposer for integrated circuit devices

#8 | 2008-10-16
US20080251932A1
Electricity

Method of forming through-silicon vias with stress buffer collars and resulting devices

#9 | 2007-10-04
US20070231953A1
Electricity

Flexible interconnect pattern on semiconductor package

#10 | 2007-07-05
US20070152194A1
Electricity

Horizontal Carbon Nanotubes by Vertical Growth and Rolling

#11 | 2007-04-26
US20070090517A1
Electricity

Stacked die package with thermally conductive block embedded in substrate

#12 | 2007-01-04
US20070001266A1
Electricity

Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion

#13 | 2007-01-04
US20070000592A1
Electricity

Apparatus and method to operate on one or more attach sites in die package assembly

#14 | 2006-12-28
US20060290002A1
Electricity

Method of forming through-silicon vias with stress buffer collars and resulting devices

#15 | 2006-11-09
US20060252354A1
Performing operations; transporting

Methods and devices for supporting substrates using fluids

#16 | 2006-08-24
US20060189121A1
Electricity

Thin silicon based substrate

#17 | 2006-04-13
US20060079079A1
Electricity

Method of manufacturing of thin based substrate

#18 | 2006-03-02
US20060046433A1
Electricity

Thinning semiconductor wafers

#19 | 2006-02-23
US20060038303A1
Electricity

Etched interposer for integrated circuit devices

InventorID:

248060 ⎘