Beaverton, Oregon
United States
60
2026-06-25
The entities that hold a legal rights for patent applications filed by inventor Phan Anh:
Anh Phan from Beaverton, US has applied for patents for these inventions. The list has both pending applications and granted patents:
THERMAL MANAGEMENT STRUCTURES INTEGRATED IN SEMICONDUCTOR DEVICES
#2 | 2025-09-25TRANSISTOR ASSEMBLIES WITH PATTERNED BACK SIDE-FILLED ISOLATION REGIONS
#3 | 2025-06-26AIR-GAPPED ISOLATION WALLS
#4 | 2025-06-26RECESSED OXIDE AND SEAM-FIRST ETCH FOR AIR-GAPPED ISOLATION WALLS
#5 | 2025-03-20AIR GAP INSULATION IN PLACE OF GATE SPACERS
#6 | 2025-03-20AIR GAP INSULATION IN PLACE OF GATE SPACERS
#7 | 2024-11-07BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
#8 | 2024-07-11STACKED FORKSHEET TRANSISTORS
#9 | 2024-06-06INTEGRATED CIRCUIT STRUCTURES WITH CAVITY SPACERS
#10 | 2024-05-16Sideways vias in isolation areas to contact interior layers in stacked devices
#11 | 2024-05-02Stacked source-drain-gate connection and process for forming such
#12 | 2024-02-08GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BOTTOM-UP OXIDATION APPROACH
#13 | 2023-11-23Forming an oxide volume within a fin
#14 | 2023-11-16GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING MULTIPLE BOTTOM-UP OXIDATION APPROACHES
#15 | 2023-11-02Interconnect techniques for electrically connecting source/drain regions of stacked transistors
#16 | 2023-07-27Stacked source-drain-gate connection and process for forming such
#17 | 2023-06-01Stacked trigate transistors with dielectric isolation and process for forming such
#18 | 2023-03-23CMOS ARCHITECTURE WITH THERMALLY STABLE SILICIDE GATE WORKFUNCTION METAL
#19 | 2022-11-03Backside contacts for semiconductor devices
#20 | 2022-11-03Isolation wall stressor structures to improve channel stress and their methods of fabrication
#21 | 2022-10-27Metallization structures for stacked device connectivity and their methods of fabrication
#22 | 2022-08-04Leave-behind protective layer having secondary purpose
#23 | 2022-03-31Vertically stacked transistor devices with isolation wall structures containing an electrical conductor
#24 | 2021-12-30Stacked forksheet transistors
#25 | 2021-09-30Stacked transistor structures with asymmetrical terminal interconnects
#26 | 2021-03-25Stacked transistors with Si PMOS and high mobility thin film transistor NMOS
#27 | 2021-02-25III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts
#28 | 2020-12-31Stacked source-drain-gate connection and process for forming such
#29 | 2020-12-31DEVICES WITH AIR GAPPING BETWEEN STACKED TRANSISTORS AND PROCESS FOR PROVIDING SUCH
#30 | 2020-12-31Stacked trigate transistors with dielectric isolation between first and second semiconductor fins
#31 | 2020-12-31Sidewall interconnect metallization structures for integrated circuit devices
#32 | 2020-12-31Sideways vias in isolation areas to contact interior layers in stacked devices
#33 | 2020-12-31MEMORY DEVICES WITH A LOGIC REGION BETWEEN MEMORY REGIONS
#34 | 2020-12-31Forming an oxide volume within a fin
#35 | 2020-12-31Epitaxial layer with substantially parallel sides
#36 | 2020-12-17Metallization structures for stacked device connectivity and their methods of fabrication
#37 | 2020-09-24Isolation wall stressor structures to improve channel stress and their methods of fabrication
#38 | 2020-09-17STACKED TRANSISTORS WITH DIFFERENT CRYSTAL ORIENTATIONS IN DIFFERENT DEVICE STRATA
#39 | 2020-09-17Stacked transistors having device strata with different channel widths
#40 | 2020-09-17Backside contacts for semiconductor devices
#41 | 2020-09-17STACKED TRANSISTORS WITH DIELECTRIC BETWEEN SOURCE/DRAIN MATERIALS OF DIFFERENT STRATA
#42 | 2020-08-27Vertically stacked transistor devices with isolation wall structures containing an electrical conductor
#43 | 2020-08-20Stacked transistors with dielectric between channels of different device strata
#44 | 2020-08-13Vertical diode in stacked transistor architecture
#45 | 2020-08-13Self-aligned local interconnects
#46 | 2020-07-23Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor
#47 | 2020-07-09Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach
#48 | 2020-07-09Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches
#49 | 2020-07-02SELF-ALIGNED STACKED GE/SI CMOS TRANSISTOR STRUCTURE
#50 | 2020-07-02Three dimensional integrated circuits with stacked transistors
#51 | 2020-06-18Transistors on heterogeneous bonding layers
#52 | 2020-04-02Stacked transistor architecture including nanowire or nanoribbon thin film transistors
#53 | 2020-03-26Vertically stacked CMOS with upfront M0 interconnect
#54 | 2020-03-26Stacked nanowire transistor structure with different channel geometries for stress
#55 | 2020-01-02Transistors stacked on front-end p-type transistors
#56 | 2020-01-02Pedestal fin structure for stacked transistor integration
#57 | 2020-01-02Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure
#58 | 2020-01-02Leave-behind protective layer having secondary purpose
#59 | 2020-01-02Interconnect techniques for electrically connecting source/drain regions of stacked transistors
#60 | 2019-06-27Stacked transistors with different gate lengths in different device strata
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