Folsom, California
United States
34
2026-04-02
The entities that hold a legal rights for patent applications filed by inventor Gurram Chandra:
Chandra Gurram from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:
UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
#2 | 2026-02-05GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A GRAPHICS ENVIRONMENT
#3 | 2026-01-08SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY
#4 | 2025-12-25REGISTER FILE FOR SYSTOLIC ARRAY
#5 | 2025-06-19USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION
#6 | 2025-06-19MULTIPLE REGISTER ALLOCATION SIZES FOR THREADS
#7 | 2025-04-10SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
#8 | 2025-04-10DUAL PIPELINE PARALLEL SYSTOLIC ARRAY
#9 | 2024-12-26SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS
#10 | 2024-10-31GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUCT ACCUMULATE INSTRUCTION FOR HYBRID FLOATING POINT FORMAT
#11 | 2024-09-26UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
#12 | 2023-11-16Computing efficient cross channel operations in parallel computing machines using systolic arrays
#13 | 2023-09-07Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
#14 | 2023-06-22Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
#15 | 2023-03-23GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A GRAPHICS ENVIRONMENT
#16 | 2022-12-29Dual pipeline parallel systolic array
#17 | 2022-12-29Systolic array of arbitrary physical and logical depth
#18 | 2022-12-29Using sparsity metadata to reduce systolic array power consumption
#19 | 2022-12-29Multiple register allocation sizes for threads
#20 | 2022-12-29REGISTER FILE FOR SYSTOLIC ARRAY
#21 | 2022-12-29SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY
#22 | 2022-11-17Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
#23 | 2022-06-09SYSTEMS AND METHODS FOR REDUCING REGISTER BANK CONFLICTS BASED ON SOFTWARE HINT AND HARDWARE THREAD SWITCH
#24 | 2022-05-19Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
#25 | 2022-04-28Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
#26 | 2022-02-24Computing efficient cross channel operations in parallel computing machines using systolic arrays
#27 | 2021-11-25Computing efficient cross channel operations in parallel computing machines using systolic arrays
#28 | 2021-11-11Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
#29 | 2021-11-11COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS
#30 | 2021-10-07Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
#31 | 2021-03-18Utilizing structured sparsity in systolic arrays
#32 | 2020-01-02Register bank conflict reduction for multi-threaded processor
#33 | 2019-08-29Systems and methods for reducing register bank conflicts based on a software hint bit causing a hardware thread switch
#34 | 2019-07-04Resource load balancing based on usage and power limits
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