Inventor profile of:

Sriram MUTHUKUMAR

City:

Chandler, Arizona

Country:

United States

Published Applications:

27

Last publication date:

2019-05-16

Top Assignees for applications by Sriram MUTHUKUMAR

The entities that hold a legal rights for patent applications filed by inventor MUTHUKUMAR Sriram:

Recent patent applications by MUTHUKUMAR Sriram

Sriram MUTHUKUMAR from Chandler, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-05-16
US20190148275A1
Electricity

Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

#2 | 2016-08-25
US20160247774A1
Electricity

Integrated WLUF and SOD process

#3 | 2014-01-02
US20140001631A1
Electricity

Integrated WLUF and SOD process

#4 | 2013-05-23
US20130127054A1
Electricity

Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

#5 | 2012-07-26
US20120187583A1
Electricity

Methods and apparatuses to stiffen integrated circuit package

#6 | 2011-06-23
US20110147912A1
Electricity

Methods and apparatuses to stiffen integrated circuit package

#7 | 2011-03-24
US20110067236A1
Electricity

Methods for making multi-chip packaging using an interposer

#8 | 2010-12-30
US20100327419A1
Electricity

Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

#9 | 2010-12-02
US20100301492A1
Electricity

Method of stiffening coreless package substrate

#10 | 2010-09-23
US20100237505A1
Electricity

Metal-metal bonding of compliant interconnect

#11 | 2010-08-19
US20100207265A1
Electricity

Method of stiffening coreless package substrate

#12 | 2008-12-11
US20080303159A1
Electricity

Thin silicon based substrate

#13 | 2008-12-04
US20080295329A1
Electricity

Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias

#14 | 2008-12-04
US20080295325A1
Electricity

Multi-chip packaging using an interposer with through-vias

#15 | 2008-09-11
US20080217183A1
Chemistry; metallurgy

Electropolishing metal features on a semiconductor wafer

#16 | 2008-01-31
US20080023791A1
Electricity

HIGH PERFORMANCE INTEGRATED INDUCTOR

#17 | 2007-12-20
US20070290362A1
Electricity

INTEGRATED INDUCTORS AND COMPLIANT INTERCONNECTS FOR SEMICONDUCTOR PACKAGING

#18 | 2006-12-28
US20060290000A1
Electricity

Composite metal layer formed using metal nanocrystalline particles in an electroplating bath

#19 | 2006-12-21
US20060286487A1
Physics

Process for coating thick resist over polymer features

#20 | 2006-11-30
US20060270065A1
Electricity

High performance integrated inductor

#21 | 2006-11-23
US20060264021A1
Electricity

Offset solder bump method and apparatus

#22 | 2006-08-24
US20060189121A1
Electricity

Thin silicon based substrate

#23 | 2006-04-27
US20060087032A1
Electricity

Compliant interconnects for semiconductors and micromachines

#24 | 2006-04-13
US20060079079A1
Electricity

Method of manufacturing of thin based substrate

#25 | 2006-02-23
US20060038289A1
Electricity

Integrated inductors and compliant interconnects for semiconductor packaging

#26 | 2006-02-16
US20060033172A1
Electricity

Metal-metal bonding of compliant interconnect

#27 | 2005-10-27
US20050239275A1
Electricity

Compliant multi-composition interconnects

InventorID:

256426 ⎘