Inventor profile of:

Deepak Raghu

City:

Milpitas, California

Country:

United States

Published Applications:

24

Last publication date:

2017-07-27

Top Assignees for applications by Deepak Raghu

The entities that hold a legal rights for patent applications filed by inventor Raghu Deepak:

Recent patent applications by Raghu Deepak

Deepak Raghu from Milpitas, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2017-07-27
US20170213599A1
Physics

Proxy wordline stress for read disturb detection

#2 | 2017-04-20
US20170109040A1
Physics

Systems and methods for sampling data at a non-volatile memory system

#3 | 2017-03-16
US20170076811A1
Physics

Proxy wordline stress for read disturb detection

#4 | 2016-05-05
US20160124679A1
Physics

Read scrub with adaptive counter management

#5 | 2016-02-25
US20160055918A1
Physics

Zoned erase verify in three dimensional nonvolatile memory

#6 | 2015-12-29
US14596751
Physics

Techniques for detection and treating memory hole to local interconnect marginality defects

#7 | 2015-11-19
US20150331626A1
Physics

In-situ block folding for nonvolatile memory

#8 | 2015-06-11
US20150162088A1
Physics

String dependent parameter setup

#9 | 2015-06-11
US20150162087A1
Physics

Write scheme for charge trapping memory

#10 | 2015-06-11
US20150162086A1
Physics

Systems and methods for partial page programming of multi level cells

#11 | 2015-04-30
US20150121157A1
Physics

Selection of data for redundancy calculation by likely error rate

#12 | 2015-04-30
US20150121156A1
Physics

Block Structure Profiling in Three Dimensional Memory

#13 | 2015-04-30
US20150117099A1
Physics

Selection of data for redundancy calculation by likely error rate

#14 | 2015-04-21
US14289243
Physics

String dependent parameter setup

#15 | 2015-03-26
US20150085574A1
Physics

Back gate operation with elevated threshold voltage

#16 | 2015-03-05
US20150067419A1
Physics

Bad block reconfiguration in nonvolatile memory

#17 | 2015-03-05
US20150063028A1
Physics

Bad block reconfiguration in nonvolatile memory

#18 | 2015-02-24
US14284708
Physics

Systems and methods for partial page programming of multi level cells

#19 | 2015-01-06
US14044143
Physics

Three-dimensional NAND memory with adaptive erase

#20 | 2014-12-02
US14289230
Physics

Write scheme for charge trapping memory

#21 | 2014-12-02
US14283919
Physics

Three-dimensional NAND memory with adaptive erase

#22 | 2014-12-02
US14283912
Physics

Block structure profiling in three dimensional memory

#23 | 2014-11-11
US14278747
Physics

In-situ block folding for nonvolatile memory

#24 | 2013-05-23
US20130128665A1
Physics

Non-volatile storage with broken word line screen and data recovery

InventorID:

258949 ⎘