Inventor profile of:

Sameer Paital

City:

Chandler, Arizona

Country:

United States

Published Applications:

26

Last publication date:

2025-10-16

Top Assignees for applications by Sameer Paital

The entities that hold a legal rights for patent applications filed by inventor Paital Sameer:

Recent patent applications by Paital Sameer

Sameer Paital from Chandler, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-10-16
US20250323166A1
Electricity

LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING

#2 | 2024-12-19
US20240421043A1
Electricity

SUBSTRATE PROCESS FLOW FOR ENABLING SUBSTRATE TO DIE HYBRID BONDING

#3 | 2024-07-18
US20240243066A1
Electricity

LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING

#4 | 2024-05-30
US20240178145A1
Electricity

LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING

#5 | 2024-04-04
US20240114623A1
Electricity

HYBRID BONDED PASSIVE INTEGRATED DEVICES ON GLASS CORE

#6 | 2024-03-14
US20240088052A1
Electricity

PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING

#7 | 2023-12-28
US20230420378A1
Electricity

PACKAGING ARCHITECTURE WITH CAVITIES FOR EMBEDDED INTERCONNECT BRIDGES

#8 | 2023-12-28
US20230420357A1
Electricity

SILICON NITRIDE LAYER UNDER A COPPER PAD

#9 | 2023-05-11
US20230146165A1
Electricity

SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS AND METHOD OF MAKING

#10 | 2023-03-23
US20230092903A1
Electricity

METHODS AND APPARATUS TO EMBED HOST DIES IN A SUBSTRATE

#11 | 2023-03-23
US20230092242A1
Electricity

DIELECTRIC LAYER SEPARATING A METAL PAD OF A THROUGH GLASS VIA FROM A SURFACE OF THE GLASS

#12 | 2023-03-23
US20230088392A1
Electricity

THERMALLY CONDUCTIVE SLEEVES AROUND TGVS FOR IMPROVED HEAT DISSIPATION IN GLASS CORE SUBSTRATES OR GLASS INTERPOSERS

#13 | 2023-03-23
US20230087838A1
Electricity

PROTECTIVE COATING ON AN EDGE OF A GLASS CORE

#14 | 2023-03-16
US20230085411A1
Electricity

GLASS CORE WITH CAVITY STRUCTURE FOR HETEROGENEOUS PACKAGING ARCHITECTURE

#15 | 2022-08-11
US20220254559A1
Electricity

Substrate embedded magnetic core inductors and method of making

#16 | 2022-07-14
US20220223527A1
Electricity

Lithographic cavity formation to enable EMIB bump pitch scaling

#17 | 2022-05-19
US20220155539A1
Physics

HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES

#18 | 2021-03-25
US20210091030A1
Electricity

Electroless-catalyst doped-mold materials for integrated-circuit die packaging architectures

#19 | 2020-10-29
US20200343049A1
Electricity

Method to form high capacitance thin film capacitors (TFCs) as embedded passives in organic substrate packages

#20 | 2020-10-01
US20200312771A1
Electricity

Patternable die attach materials and processes for patterning

#21 | 2020-03-19
US20200091053A1
Electricity

INTEGRATED CIRCUIT PACKAGE SUPPORTS HAVING INDUCTORS WITH MAGNETIC MATERIAL

#22 | 2020-03-12
US20200083164A1
Electricity

Selective deposition of embedded thin-film resistors for semiconductor packaging

#23 | 2020-01-02
US20200005990A1
Electricity

STRUCTURES WITHIN A SUBSTRATE LAYER TO CURE MAGNETIC PASTE

#24 | 2020-01-02
US20200005987A1
Electricity

Substrate embedded magnetic core inductors and method of making

#25 | 2019-09-26
US20190295951A1
Electricity

Lithographic cavity formation to enable EMIB bump pitch scaling

#26 | 2019-09-12
US20190279806A1
Electricity

Thin film barrier seed metallization in magnetic-plugged through hole inductor

InventorID:

2605357 ⎘