Thomas Werner

Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS

SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

Stress reduction in chip packaging by using a low-temperature chip-package connection regime

Self-aligned multiple gate transistor formed on a bulk substrate

Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime

Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding

Method of reducing contamination by providing a removable polymer protection film during microstructure processing

Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition

Fabricating vias of different size of a semiconductor device by splitting the via patterning process

Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer

Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material

HIGH-ASPECT RATIO CONTACT ELEMENT WITH SUPERIOR SHAPE IN A SEMICONDUCTOR DEVICE FOR IMPROVING LINER DEPOSITION

Microstructure device including a metallization structure with self-aligned air gaps and refilled air gap exclusion zones

Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom

Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size

Metallization system of a semiconductor device comprising extra-tapered transition vias

PERFORMANCE ENHANCEMENT IN METALLIZATION SYSTEMS OF MICROSTRUCTURE DEVICES BY INCORPORATING GRAIN SIZE INCREASING METAL FEATURES

MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH AIR GAPS FORMED COMMONLY WITH VIAS

Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer

USING A CAP LAYER IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES AS A CMP AND ETCH STOP LAYER

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

METHOD FOR REDUCING METAL IRREGULARITIES IN ADVANCED METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES

MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES

Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material

Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics

Hybrid contact structure with low aspect ratio contacts in a semiconductor device

SEMICONDUCTOR DEVICE HAVING A LOCALLY ENHANCED ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE

METHOD FOR THE PROTECTION OF METAL LAYERS AGAINST EXTERNAL CONTAMINATION

Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias

Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics

Method of forming an electrically conductive line in an integrated circuit

Method of reducing contamination by providing a removable polymer protection film during microstructure processing

Method of forming an etch indicator layer for reducing etch non-uniformities

Test structure for monitoring leakage currents in a metallization layer