Santa Clara, California
United States
18
2025-12-25
The entities that hold a legal rights for patent applications filed by inventor Evers Marius:
Marius Evers from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:
CORE ISOLATION FOR ERRORS
#2 | 2025-10-14Protection against branch target buffer poisoning by a management layer
#3 | 2024-04-18Processor-guided execution of offloaded instructions using fixed function operations
#4 | 2023-10-24Protection against branch target buffer poisoning by a management layer
#5 | 2022-06-16Processor-guided execution of offloaded instructions using fixed function operations
#6 | 2021-12-02Merged branch target buffer entries
#7 | 2021-06-24Using loop exit prediction to accelerate or suppress loop mode of a processor
#8 | 2021-06-10Instruction cache prefetch throttle
#9 | 2021-02-25Retaining cache entries of a processor core during a powered-down state
#10 | 2021-02-04Selectively performing ahead branch prediction based on types of branch instructions
#11 | 2020-08-27Processor with accelerated lock instruction operation
#12 | 2020-03-19Using loop exit prediction to accelerate or suppress loop mode of a processor
#13 | 2020-01-30Branch target buffer with early return prediction
#14 | 2020-01-30Using return address predictor to speed up control stack return address verification
#15 | 2019-12-26Low latency synchronization for operation cache and instruction cache fetching and decoding instructions
#16 | 2019-12-19Selectively performing ahead branch prediction based on types of branch instructions
#17 | 2019-12-05Storing incidental branch predictions to reduce latency of misprediction recovery
#18 | 2019-10-10Tracking stores and loads by bypassing load store units
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