Neubiberg
Germany
77
2026-01-29
The entities that hold a legal rights for patent applications filed by inventor Mayer Peter:
Peter Mayer from Neubiberg, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
ERROR CONTROL FOR FUSE ARRAYS
#2 | 2026-01-22MULTIPLE FUSE COMPARISON FOR EARLY FAILURE CHECK
#3 | 2025-10-02REDUNDANCY TECHNIQUES FOR MULTI-CHANNEL MEMORY DEVICES
#4 | 2025-08-28ACTIVATE COMMANDS FOR MEMORY PREPARATION
#5 | 2025-08-21CHANNEL MODULATION FOR A MEMORY DEVICE
#6 | 2025-08-14DYNAMIC CONTROL OF ERROR MANAGEMENT AND SIGNALING
#7 | 2025-03-27CYCLIC REDUNDANCY CHECK COMPARISON FOR ERROR DETECTION
#8 | 2025-02-06DRIVE STRENGTH CALIBRATION FOR MULTI-LEVEL SIGNALING
#9 | 2025-01-09TECHNIQUES FOR DATA PATH ADDRESS PROTECTION
#10 | 2025-01-09TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK
#11 | 2025-01-09LEARNED TEMPERATURE COMPENSATION
#12 | 2024-12-12MULTI-DRIVER SIGNALING
#13 | 2024-12-05TEMPERATURE-BASED MEMORY MANAGEMENT
#14 | 2024-11-28OFFSET CANCELLATION
#15 | 2024-05-30Dynamic control of error management and signaling
#16 | 2024-04-18Channel modulation for a memory device
#17 | 2024-03-21Transmission failure feedback schemes for reducing crosstalk
#18 | 2023-11-30Drive strength calibration for multi-level signaling
#19 | 2023-10-26Tracking a reference voltage after boot-up
#20 | 2023-06-22Signal path biasing in a memory system
#21 | 2023-05-25Activate commands for memory preparation
#22 | 2023-02-16Activate commands for memory preparation
#23 | 2023-02-02Dynamic control of error management and signaling
#24 | 2022-12-08CONFIGURING COMMAND/ADDRESS CHANNEL FOR MEMORY
#25 | 2022-12-01Multi-level signaling for a memory device
#26 | 2022-11-24Drive strength calibration for multi-level signaling
#27 | 2022-11-17Techniques for communicating multi-level signals
#28 | 2022-11-03Multi-driver signaling
#29 | 2022-10-20Channel modulation for a memory device
#30 | 2022-07-19Techniques for communicating multi-level signals
#31 | 2022-06-30Temperature-based memory management
#32 | 2022-06-02Offset cancellation
#33 | 2022-06-02Controlled heating of a memory device
#34 | 2022-04-21Mode-dependent heating of a memory device
#35 | 2022-03-31Transmission failure feedback schemes for reducing crosstalk
#36 | 2022-02-24Multi-level receiver with termination-off mode
#37 | 2022-01-27Dynamically configuring transmission lines of a bus
#38 | 2022-01-13Dynamic control of error management and signaling
#39 | 2022-01-06Reporting control information errors
#40 | 2021-12-23Receive-side crosstalk cancelation
#41 | 2021-10-14Drive strength calibration for multi-level signaling
#42 | 2021-10-14Training procedure for receivers associated with a memory device
#43 | 2021-03-25Controlled heating of a memory device
#44 | 2021-03-18Pre-distortion for multi-level signaling
#45 | 2020-12-08Multiple memory die techniques
#46 | 2020-10-22Method and apparatus for signal path biasing in a memory system
#47 | 2020-09-17Receive-side crosstalk cancelation
#48 | 2020-07-23Channel modulation for a memory device
#49 | 2020-06-25Reporting control information errors
#50 | 2020-06-25Memory device low power mode
#51 | 2020-06-18Dynamic control of error management and signaling
#52 | 2020-06-11Multi-level signaling for a memory device
#53 | 2020-05-28Configuring command/address channel for memory
#54 | 2020-05-21Temperature-based memory management
#55 | 2020-04-23Mode-dependent heating of a memory device
#56 | 2020-04-23Multi-level receiver with termination-off mode
#57 | 2020-04-16Adapting channel current
#58 | 2020-04-16Offset cancellation
#59 | 2020-04-09Dynamically configuring transmission lines of a bus
#60 | 2020-02-27Pre-distortion for multi-level signaling
#61 | 2020-02-27Drive strength calibration for multi-level signaling
#62 | 2020-02-27Training procedure for receivers associated with a memory device
#63 | 2020-02-27Transmission failure feedback schemes for reducing crosstalk
#64 | 2019-10-17Clock characteristic determination
#65 | 2008-08-07METHODS AND SYSTEMS FOR STORING DATA BASED ON A RELIABILITY REQUIREMENT
#66 | 2008-07-31Asynchronous data transmission
#67 | 2008-07-31OPTICAL MULTI MODE TRANSMISSION BETWEEN A PROCESSOR AND A SET OF MEMORIES
#68 | 2008-05-22Display with memory for storing picture data
#69 | 2008-04-03METHOD AND APPARATUS FOR REFRESHING MEMORY CELLS OF A MEMORY
#70 | 2008-03-13Method and apparatus for sending data from a memory
#71 | 2008-03-13Memory circuit, a dynamic random access memory, a system comprising a memory and a floating point unit and a method for storing digital data
#72 | 2008-03-06SYSTEM AND METHOD OF CONNECTING A PROCESSING UNIT WITH A MEMORY UNIT
#73 | 2008-03-06MEMORY WITH MEMORY BANKS AND MODE REGISTERS AND METHOD OF OPERATING A MEMORY
#74 | 2008-01-17Apparatus and method for controlling a driver strength
#75 | 2005-03-22Configuration and method for checking an address generator
#76 | 2005-02-10Test method, test receptacle and test arrangement for high-speed semiconductor memory devices
#77 | 2005-02-03Test method and apparatus for high-speed semiconductor memory devices
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