Robert MAY

GLASS ETCH PROTECTION AND SEWARE REDUCTION BY COATING PROTECTION

FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH

LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING

DIE AND CONDUCTIVE VIAS EMBEDDED IN A SUBSTRATE

DIE WITHIN A HOLE IN A SUBSTRATE CORE ATTACHED TO METAL FEATURES OVER THE HOLE

VERTICALLY EMBEDDED PRE-FORMED DEEP TRENCH CAPACITOR MODULES

ANISOTROPIC CONDUCTIVE CONNECTIONS FOR INTERCONNECT BRIDGES AND RELATED METHODS

DIE EMBEDDED IN GLASS LAYER WITH TWO-SIDE CONNECTIVITY

INTEGRATED CIRCUIT PACKAGE SUPPORTS

METHODS AND APPARATUS FOR EDGE PROTECTED GLASS CORES

CO-PACKAGING OF PHOTONIC & ELECTRONIC INTEGRATED CIRCUIT DIE

PHOTONIC INTEGRATED CIRCUIT PACKAGES AND METHODS OF MANUFACTURING THE SAME

LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING

PHOTONIC INTEGRATED CIRCUITS WITH GLASS CORES

LITHOGRAPHIC PROCESSES FOR MAKING POLYMER-BASED ELEMENTS

LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING

Integrated circuit package supports

EMIB patch on glass laminate substrate

FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH

Surface finishes with low RBTV for fine and mixed bump pitch architectures

Magneto-optical Kerr effect interconnects for photonic packaging

Lithographic cavity formation to enable EMIB bump pitch scaling

Integrated circuit package supports

FIRST LAYER INTERCONNECT FIRST ON CARRIER APPROACH FOR EMIB PATCH

EMIB patch on glass laminate substrate

First layer interconnect first on carrier approach for EMIB patch

Subtractive etch resolution implementing a functional thin metal resist

Surface finishes with low rBTV for fine and mixed bump pitch architectures

Integrated circuit package supports

Lithographic cavity formation to enable EMIB bump pitch scaling