Inventor profile of:

Anton deVilliers

City:

Albany, New York

Country:

United States

Published Applications:

18

Last publication date:

2025-12-25

Top Assignees for applications by Anton deVilliers

The entities that hold a legal rights for patent applications filed by inventor deVilliers Anton:

Recent patent applications by deVilliers Anton

Anton deVilliers from Albany, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-12-25
US20250391808A1
Electricity

WAFER OVERLAY REGISTRATION IN HYBRID BONDING

#2 | 2025-10-02
US20250308951A1
Electricity

DIE TO WAFER BONDING METHOD AND APPARATUS WITH THERMAL CONTACTLESS DIE SHAPE CONTROL

#3 | 2025-10-02
US20250308949A1
Electricity

DIE TO WAFER BONDING METHOD AND APPARATUS WITH THERMAL CONTACT DIE SHAPE CONTROL

#4 | 2025-10-02
US20250308902A1
Electricity

USING LASER BASED SYSTEM FOR MEAN OF SHAPING OF UNSINGULATED & SINGULATED DIES BY SUBSTRATE LATTICE MANIPULATION

#5 | 2025-10-02
US20250306463A1
Physics

PATTERNING A SUBSTRATE USING A MULTI-PATTERNING TECHNIQUE

#6 | 2025-09-11
US20250285884A1
Electricity

Wet Processing Systems Having Novel Wafer Chuck Designs For Retaining A Processing Liquid On A Surface Of A Semiconductor Substrate

#7 | 2025-09-11
US20250285883A1
Electricity

Novel Wafer Chuck Designs And Methods For Retaining A Processing Liquid On A Surface Of A Semiconductor Wafer

#8 | 2025-04-17
US20250123090A1
Physics

DEVICE AND METHOD FOR DETERMINING WAFER BOW

#9 | 2025-02-27
US20250068823A1
Physics

CIRCUIT DESIGN MODELING FOR BONDING INTEGRATED CIRCUITS

#10 | 2024-08-29
US20240289529A1
Physics

METHOD FOR CELL LAYOUT

#11 | 2024-06-20
US20240203778A1
Electricity

APPARATUS AND METHOD FOR WAFER ALIGNMENT

#12 | 2021-08-05
US20210242351A1
Electricity

EFFICIENT THREE-DIMENSIONAL DESIGN FOR LOGIC APPLICATIONS USING VARIABLE VOLTAGE THRESHOLD THREE-DIMENSIONAL CMOS DEVICES

#13 | 2021-08-05
US20210242020A1
Electricity

Multiple patterning processes

#14 | 2021-04-01
US20210098294A1
Electricity

Reverse contact and silicide process for three-dimensional semiconductor devices

#15 | 2021-02-04
US20210035981A1
Electricity

Method and process for forming memory hole patterns

#16 | 2020-05-14
US20200152473A1
Electricity

Method for forming and using stress-tuned silicon oxide films in semiconductor device patterning

#17 | 2019-09-19
US20190287795A1
Electricity

Critical dimension correction via calibrated trim dosing

#18 | 2018-11-29
US20180342410A1
Electricity

Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer

InventorID:

2732963 ⎘